mcf5272 Freescale Semiconductor, Inc, mcf5272 Datasheet - Page 254

• Manufacturer Part Number: mcf5272
• Description: Mcf5272 Coldfire Integrated Microprocessor User
• Manufacturer: Freescale Semiconductor, Inc

Programming Model
11.5.22 Initialization Sequence
This section describes which registers and RAM locations are reset due to hardware reset,
which are reset due to the FEC reset, and what locations the user must initialize before
enabling the FEC.
As soon as the FEC is initialized and enabled, it operates autonomously. Typically, the
driver writes only to RDAR, TDAR, and EIR during operation.
11.5.22.1 Hardware Initialization
In the FEC, hardware resets only those registers that generate interrupts to the MCF5272
processor or cause conflict on bidirectional buses. The registers are reset due to a hardware
reset.
Other registers reset whenever the ETHER_EN bit is cleared. Clearing ETHER_EN
immediately stops all DMA and transmit activity after a bad CRC is sent, as shown in
Table 11-31
11.5.23 User Initialization (Prior to Asserting ETHER_EN)
The user must initialize portions the FEC prior to setting the ETHER_EN bit. The exact
11-30
System
User
User/System
31–11
10–4
Bits
3–0
System
User
Table 11-29. EMRBR Field Descriptions
Table 11-30. Hardware Initialization
R_BUFF_SIZE
Table 11-31. ETHER_EN = 0
Name
XMIT block
DMA block
—
—
Register/Machine
MII State Machine
Location
RDAR
TDAR
MCF5272 User’s Manual
MSCR
EIMR
ECR
EIR
Reserved, should be cleared.
Reserved, should be cleared.
Receive buffer size.
Prevent conflict on MMFR
All DMA activity is terminated
Description
Transmission is Aborted
Reset Value
Cleared
Cleared
Cleared
Cleared
Cleared
Cleared
Effect
MOTOROLA