mcf5272 Freescale Semiconductor, Inc, mcf5272 Datasheet - Page 391

• Manufacturer Part Number: mcf5272
• Description: Mcf5272 Coldfire Integrated Microprocessor User
• Manufacturer: Freescale Semiconductor, Inc

MOTOROLA
16.5.5 Bus Operation
This section describes bus operation during read, write, and interrupt acknowledge cycles
to the UART module.
16.5.5.1 Read Cycles
The UART module responds to reads with byte data. Reserved registers return zeros.
16.5.5.2 Write Cycles
The UART module accepts write data as bytes. Write cycles to read-only or reserved
registers complete normally without exception processing, but data is ignored.
16.5.5.3 Interrupt Acknowledge Cycles
An internal interrupt request signal notifies the interrupt controller of any unmasked
interrupt conditions. The interrupt priority level is programmed in ICR2.
16.5.6 Programming
The software flowchart, Figure 16-31, consists of the following:
• UART module initialization—These routines consist of SINIT and CHCHK (sheets
• I/O driver routine—This routine (sheets 4 and 5) consists of INCH, the terminal
• Interrupt handling—Consists of SIRQ (sheet 4), which is executed after the UART
1 and 2). Before SINIT is called at system initialization, the calling routine allocates
2 words on the system stack. On return to the calling routine, SINIT passes UART
status data on the stack. If SINIT finds no errors, the transmitter and receiver are
enabled. SINIT calls CHCHK to perform the checks. When called, SINIT places the
UART in local loop-back mode and checks for the following errors:
— Transmitter never ready
— Receiver never ready
— Parity error
— Incorrect character received
input character routine which gets a character from the receiver, and OUTCH, which
sends a character to the transmitter.
module generates an interrupt caused by a change-in-break (beginning of a break).
SIRQ then clears the interrupt source, waits for the next change-in-break interrupt
(end of break), clears the interrupt source again, then returns from exception
processing to the system monitor.
Chapter 16. UART Modules
Operation
16-31