mcf5272 Freescale Semiconductor, Inc, mcf5272 Datasheet - Page 186

• Manufacturer Part Number: mcf5272
• Description: Mcf5272 Coldfire Integrated Microprocessor User
• Manufacturer: Freescale Semiconductor, Inc

Interrupt Controller Registers
Table 7-6 describes PIWR fields.
7.2.6 Programmable Interrupt Vector Register (PIVR)
The programmable interrupt vector register (PIVR), Figure 7-9, specifies the vector
numbers the interrupt controller returns in response to interrupt acknowledge cycles for the
various peripherals and discrete interrupt sources.
Pending interrupts are presented to the processor core in order of priority from highest to
lowest. The core responds to an interrupt request by initiating an interrupt acknowledge
cycle to receive a vector number, which allows the core to locate the interrupt’s service
routine. The interrupt controller is able to identify the source of the highest priority
interrupt that is being acknowledged and provide the interrupt vector to the core. The three
most significant bits of the interrupt vector are programmed by the user in the PIVR. The
lower five bits are provided by the interrupt controller, depending on the source, as shown
in Table 7-7.
7-8
31–4
Bits
3–0
Address
Reset
Reset
Reset
Reset
Field
Field
Field
Field
R/W
R/W
R/W
R/W
Field
—
—
UART1
Figure 7-8. Programmable Interrupt Wakeup Register (PIWR)
USB4
QSPI
INT1
31
23
15
7
0 Interrupt cannot wake up the CPU when interrupt source is active.
1 Interrupt wakes up the CPU from low-power modes.
Reserved, should be cleared.
UART2
USB5
INT2
INT5
30
22
14
6
Table 7-6. PIWR Field Descriptions
PLI_P
USB6
INT3
INT6
29
21
13
5
MCF5272 User’s Manual
SWTO
PLI_A
USB7
INT4
28
20
12
4
MBAR+0x038
1111_1111
1111_1111
1111_1111
1111_0000
R/W
R/W
R/W
R/W
Description
TMR0
USB0
DMA
27
19
11
3
TMR1
USB1
ERx
26
18
10
—
TMR2
USB2
ETx
25
17
9
MOTOROLA
TMR3
ENTC
USB3
24
16
8
0