mcf5272 Freescale Semiconductor, Inc, mcf5272 Datasheet - Page 322

• Manufacturer Part Number: mcf5272
• Description: Mcf5272 Coldfire Integrated Microprocessor User
• Manufacturer: Freescale Semiconductor, Inc

PLIC Registers
13.5.14 GCI Monitor Channel Transmit Abort Register
All bits in this register are read/write and are cleared on hardware or software reset.
The PGMTA register contains the abort control bits for each of the four ports on the
MCF5272 for the transmit monitor channel.
15–10
13-26
Reset
Bits
7–0
Field
Addr
R/W
9
8
Figure 13-25. GCI Monitor Channel Transmit Registers (P0GMT–P3GMT)
Name
15
Figure 13-26. GCI Monitor Channel Transmit Abort Register (PGMTA)
—
R
M
L
(PGMTA)
Reserved, should be cleared.
Last.
0 Default reset value
1 Set by the CPU. Indicates to the monitor channel controller to transmit the end of message signal
Ready.
0 Default reset value.
1 Set by the CPU. Indicate to the monitor channel controller that a byte of data is ready for
Monitor channel data byte. Written by the CPU when a byte is ready for transmission.
Reset
on the E bit. Both PnGMT[L] and PnGMT[R] must be set for the monitor channel controller to send
the end of message signal. PnGMT[M7:0] are ignored and 0xFF is sent with the end of message
condition necessitating sending the monitor channel information using PnGMT[R] to control the
monitor channel transmitter, followed at the end of the frame by setting PnGMT[L] and PnGMT[R].
The L bit is automatically cleared by the GCI controller.
transmission. Automatically cleared by the GCI controller when it generates a transmit
acknowledge (ACK bit in PGMTS register) or when the L bit is reset.
Field
Addr
R/W
MBAR + 0x368 (P0GMT); 0x36A (P1GMT); 0x36C (P2GMT); 0x36E (P3GMT)
Table 13-8. P0GMT–P3GMT Field Descriptions
—
AR3
7
AR2
6
10
MCF5272 User’s Manual
AR1
5
0000_0000_0000_0000
L
9
MBAR + 0x372
AR0
Read/Write
0000_0000
Read/Write
4
R
8
Description
7
3
—
M
0
MOTOROLA
0