mcf5272 Freescale Semiconductor, Inc, mcf5272 Datasheet - Page 136

• Manufacturer Part Number: mcf5272
• Description: Mcf5272 Coldfire Integrated Microprocessor User
• Manufacturer: Freescale Semiconductor, Inc

DRc[4–0]
Programming Model
A write to TDR clears the CSR trigger status bits, CSR[BSTAT].
Table 5-14 describes TDR fields.
5-14
31–30
15–14
28–22
29/13
28/12
27/11
26/10
12–6
Bits
25/9
24/8
23/7
22/6
Reset
Reset
Field
Field
R/W Write only. Accessible in supervisor mode as debug control register 0x07 using the WDEBUG instruction and
through the BDM port using the
Name
31
15
TRC
EBL
EDx
TRC
—
—
30
14
The debug module has no hardware interlocks, so to prevent
spurious breakpoint triggers while the breakpoint registers are
being loaded, disable TDR (by clearing TDR[29,13])before
defining triggers.
Trigger response control. Determines how the processor responds to a completed trigger condition.
The trigger response is always displayed on DDATA.
00 Display on DDATA only
01 Processor halt
10 Debug interrupt
11 Reserved
Reserved, should be cleared.
Enable breakpoint. Global enable for the breakpoint trigger. Setting TDR[EBL] enables a breakpoint
trigger. Clearing it disables all breakpoints at that level.
Setting an EDx bit enables the corresponding data breakpoint condition based on the size and
placement on the processor’s local data bus. Clearing all EDx bits disables data breakpoints.
EDLW
EDWL
EDWU Upper data word.
EDLL
EDLM
EDUM
EDUU
EBL
EBL
29
13
Figure 5-11. Trigger Definition Register (TDR)
EDLW EDWL EDWU EDLL EDLM EDUM EDUU
EDLW EDWL EDWU EDLL EDLM EDUM EDUU
Data longword. Entire processor’s local data bus.
Lower data word.
Lower lower data byte. Low-order byte of the low-order word.
Lower middle data byte. High-order byte of the low-order word.
Upper middle data byte. Low-order byte of the high-order word.
Upper upper data byte. High-order byte of the high-order word.
28
12
Table 5-14. TDR Field Descriptions
27
11
WDMREG
26
10
MCF5272 User’s Manual
command.
25
0000_0000_0000_0000
0000_0000_0000_0000
9
NOTE:
Second-Level Trigger
24
First-Level Trigger
8
Description
0x07
23
7
22
6
DI
DI
21
5
EAI EAR EAL EPC PCI
EAI EAR EAL EPC PCI
20
4
19
3
18
2
MOTOROLA
17
1
16
0