mcf5272 Freescale Semiconductor, Inc, mcf5272 Datasheet - Page 71

• Manufacturer Part Number: mcf5272
• Description: Mcf5272 Coldfire Integrated Microprocessor User
• Manufacturer: Freescale Semiconductor, Inc

MOTOROLA
2.1.1.2 Operand Execution Pipeline (OEP)
The OEP is a two-stage pipeline featuring a traditional RISC datapath with a register file
feeding an arithmetic/logic unit (ALU). For simple register-to-register instructions, the first
stage of the OEP performs the instruction decode and fetching of the required register
operands (OC), while the actual instruction execution is performed in the second stage
(EX).
For memory-to-register instructions, the instruction is effectively staged through the OEP
twice in the following way:
For register-to-memory operations, the stage functions (DS/OC, AG/EX) are effectively
performed simultaneously allowing single-cycle execution. For read-modify-write
instructions, the pipeline effectively combines a memory-to-register operation with a store
operation.
2.1.1.2.1 Illegal Opcode Handling
On Version 2 ColdFire implementations, only some illegal opcodes (0x0000 and 0x4AFC)
are decoded and generate an illegal instruction exception. Additionally, attempting to
execute an illegal line A or line F opcode generates unique exception types. If any other
unsupported opcode is executed, the resulting operation is undefined.
2.1.1.2.2 Hardware Multiply/Accumulate (MAC) Unit
The MAC is an optional unit in Version 2 that provides hardware support for a limited set
of digital signal processing (DSP) operations used in embedded code, while supporting the
integer multiply instructions in the ColdFire microprocessor family. The MAC features a
three-stage execution pipeline, optimized for 16 x 16 multiplies. It is tightly coupled to the
OEP, which can issue a 16 x 16 multiply with a 32-bit accumulation plus fetch a 32-bit
operand in a single cycle. A 32 x 32 multiply with a 32-bit accumulation requires three
cycles before the next instruction can be issued.
Figure 2-2 shows basic functionality of the MAC. A full set of instructions are provided for
signed and unsigned integers plus signed, fixed-point fractional input operands.
• The instruction is decoded and the components of the operand address are selected
• The operand address is generated using the execute engine (AG).
• The memory operand is fetched while any register operand is simultaneously
• The instruction is executed (EX).
(DS).
fetched (OC).
Chapter 2. ColdFire Core
Features and Enhancements
2-3