mcf5272 Freescale Semiconductor, Inc, mcf5272 Datasheet - Page 313

• Manufacturer Part Number: mcf5272
• Description: Mcf5272 Coldfire Integrated Microprocessor User
• Manufacturer: Freescale Semiconductor, Inc

MOTOROLA
Each of the four byte-addressable registers, P0DRR-P3DRR, are packed to form one 32-bit
register, PnDRR, located at MBAR + 0x320. P0DRR is located in the MSB of the PnDRR
register, P3DRR is located in the LSB of the PnDRR register.
13.5.4 B1 Data Transmit Registers (P0B1TR–P3B1TR)
All bits in these registers are read/write and are set on hardware or software reset.
The PnB1TR registers contain four frames of transmit data for channel B1. (P0B1TR is the
B1 channel transmit data for port 0, P1B1TR is B1 transmit for port 1, and so on.) The data
are packed from LSB to MSB.
These registers are aligned on long-word boundaries from MBAR + 0x328 for P0B1TR to
MBAR + 0x334 for P3B1TR. See Section 13.2.3, “GCI/IDL B- and D-Channel Bit
Alignment,” for the frame and bit alignment within the 32-bit word.
13.5.5 B2 Data Transmit Registers (P0B2TR–P3B2TR)
All bits in these registers are read/write and are set on hardware or software reset.
The PnB2TR registers contain four frames of transmit data for port n of channel B2.
(P0B2TR is the B2 channel transmit data for port 0, P1B2TR is B2 transmit for port 1, and
so on.) The data are packed from LSB to MSB.
Reset
Reset
Reset
Reset
Field
Field
Field
Field
Addr
Addr
R/W
R/W
R/W
R/W
31
15
31
15
Figure 13-16. B1 Transmit Data Registers P0B1TR–P3B1TR
Figure 13-15. D Receive Data Registers P0DRR–P3DRR
MBAR + 0x328 (P0B1TR); 0x32C (P1B1TR); 0x330 (P2B1TR); 0x334 (P3B1TR)
MBAR + 0x320 (P0DRR); 0x321 (P1DRR); 0x322 (P2DRR); 0x323 (P3DRR)
Chapter 13. Physical Layer Interface Controller (PLIC)
1111_1111
1111_1111
1111_1111
1111_1111
Frame 0
Frame 2
P0DRR
P2DRR
Read/Write
Read/Write
Read Only
Read Only
24
24
8
8
23
23
7
7
1111_1111
1111_1111
1111_1111
1111_1111
Frame 1
Frame 3
P1DRR
P3DRR
PLIC Registers
13-17
16
16
0
0