mcf5272 Freescale Semiconductor, Inc, mcf5272 Datasheet - Page 233

• Manufacturer Part Number: mcf5272
• Description: Mcf5272 Coldfire Integrated Microprocessor User
• Manufacturer: Freescale Semiconductor, Inc

FEC Frame Transmission
The effectiveness of the hash table declines as the number of addresses increases.
The hash table registers must be initialized by the user. The CRC32 polynomial to use in
computing the hash is as follows:
32
26
23
22
16
12
11
10
8
7
5
4
2
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1
11.4.5 Interpacket Gap Time
The minimum interpacket gap time for back-to-back transmission is 96 bit times. After
completing a transmission or after the backoff algorithm completes, the transmitter waits
for carrier sense to negate before starting its interpacket gap time counter. Frame
transmission may begin 96 bit times after carrier sense is negated if it stays negated for at
least 60 bit times. If carrier sense asserts during the last 36 bit times, it is ignored and a
collision will occur.
The receiver receives back-to-back frames separated by at least 28 bit times. If an
interpacket gap between receive frames is less than 28 bit times, the following frame may
be discarded by the receiver.
11.4.6 Collision Handling
If a collision occurs during transmission, the FEC continues transmitting for at least 32 bit
times, sending a JAM pattern of 32 ones. The JAM pattern follows the preamble sequence
if the collision occurs during preamble.
If a collision occurs within 64 byte times, the retry process is initiated. The transmitter waits
a random number of slot times. A slot time is 512 bit times. If a collision occurs after 64
byte times, no retransmission is performed and the end-of-frame buffer is closed with an
LC error indication.
11.4.7 Internal and External Loopback
Both internal and external loopback are supported by the FEC. In loopback mode, both of
the FIFOs are used and the FEC actually operates in a full-duplex fashion. Both internal
and external loopback are configured using combinations of RCR[LOOP].
For internal loopback, set LOOP and clear DRT. E_TxEN and E_TxER cannot assert
during internal loopback.
For external loopback, clear LOOP, set DRT, and configure the external transceiver for
loopback.
11.4.8 Ethernet Error-Handling Procedure
The FEC reports frame reception and transmission error conditions through the buffer
descriptors and the EIR register.
MOTOROLA
Chapter 11. Ethernet Module
11-9