mcf5272 Freescale Semiconductor, Inc, mcf5272 Datasheet - Page 284

• Manufacturer Part Number: mcf5272
• Description: Mcf5272 Coldfire Integrated Microprocessor User
• Manufacturer: Freescale Semiconductor, Inc

Register Description and Programming Model
12.3.2.17 USB Endpoint 1–7 Interrupt Mask Registers (EPnIMR)
Figure 12-20 shows the USB endpoint 1–7 interrupt mask register.
Table 3-16 lists field descriptions for the USB endpoint 1–7 interrupt mask register.
12-24
Bits
Reset
15–5
4–0
Field
Addr
4
3
2
1
0
R/W
Bits
Figure 12-20. USB Endpoint 1-7 Interrupt Mask Registers (EP
15
FIFO_LVL FIFO threshold level reached interrupt. Indicates that the FIFO level has risen above or
Name
UNHALT
—
Name
HALT
EOT
EOP
Table 12-15. EP
Reserved, should be cleared.
Interrupt mask. These bits are set when the user wants to activate the interrupt source for
the specific bit. Refer to Table 12-15 for a description of each interrupt source.
1 Interrupt Enabled
0 Interrupt Disabled
End of transfer interrupt. Set when the end of a transfer has been reached. An EOT
interrupt is generated when a packet with a size less than the maximum packet size or
the first zero-length packet following maximum size packets is sent or received. For OUT
endpoints, the EPDPn must be read before clearing this interrupt in order to determine
the number of bytes of remaining data in the FIFO for the last transfer. For OUT
endpoints, any packets received from the host cause a NAK response until the EOT
interrupt is cleared. For IN endpoints, the user must wait until the EOT interrupt is set
before writing the next transfer to the FIFO.
0 No interrupt pending
1 Transfer completed
End of packet interrupt. Set when a packet is successfully sent or received on endpoint n.
0 No interrupt pending
1 Packet sent or received successfully
Endpoint unhalt interrupt. Set when the endpoint n HALT_ST bit is cleared.
0 No interrupt pending
1 Endpoint n unhalted
Endpoint halt interrupt. Set when the endpoint n HALT_ST bit is set.
0 No interrupt pending
1 Endpoint n halted
fallen below the level set in the EPCTLn register for OUT or IN endpoints, respectively.
0 No interrupt pending
1 FIFO threshold level reached
MBAR + 0x1092, 0x1096, 0x109A, 0x109E, 0x10A2, 0x10A6, 0x10AA
Table 12-16. EP
—
n
MCF5272 User’s Manual
ISR Field Descriptions (Continued)
5
0000_0000_0000_0000
n
EOT_EN EOP_EN UNHALT_EN HALT_EN FIFO_LVL_EN
IMR Field Descriptions
4
Description
R/W
Description
3
2
1
n
IMR)
MOTOROLA
0