mc9s12q128 Freescale Semiconductor, Inc, mc9s12q128 Datasheet - Page 101
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mc9s12q128
Manufacturer Part Number
mc9s12q128
Description
Hcs12 Microcontrollers
Manufacturer
Freescale Semiconductor, Inc
Datasheet
1.MC9S12Q128.pdf
(644 pages)
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2.3.2.6.3
Read: Anytime.
Write: Anytime.
2.3.2.6.4
Read: Anytime.
Write: Anytime.
Freescale Semiconductor
Module Base + 0x0032
Module Base + 0x0033
DDRAD[7:0]
RDRAD[7:0]
Reset
Reset
Field
Field
7–0
7–0
W
W
R
R
DDRAD7
RDRAD7
Data Direction Port AD — This register configures port pins AD[7:0] as either input or output.
0 Associated pin is configured as input.
1 Associated pin is configured as output.
Note: Due to internal synchronization circuits, it can take up to 2 bus cycles until the correct value is read on
Reduced Drive Port AD — This register configures the drive strength of each port AD output pin as either full
or reduced. If the port is used as input this bit is ignored.
0 Full drive strength at output.
1 Associated pin drives at about 1/3 of the full drive strength.
0
0
7
7
Port AD Data Direction Register (DDRAD)
Port AD Reduced Drive Register (RDRAD)
PTAD or PTIAD registers, when changing the DDRAD register.
DDRAD6
RDRAD6
Figure 2-43. Port AD Reduced Drive Register (RDRAD)
0
Figure 2-42. Port AD Data Direction Register (DDRAD)
0
6
6
Table 2-34. DDRAD Field Descriptions
Table 2-35. RDRAD Field Descriptions
DDRAD5
RDRAD5
0
0
5
5
MC9S12Q128
DDRAD4
RDRAD4
Rev 1.09
0
0
4
4
Description
Description
Chapter 2 Port Integration Module (PIM9C32) Block Description
DDRAD3
RDRAD3
0
0
3
3
DDRAD2
RDRAD2
0
0
2
2
DDRAD1
RDRAD1
0
0
1
1
DDRAD0
RDRAD0
0
0
0
0
101
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