mc9s12q128 Freescale Semiconductor, Inc, mc9s12q128 Datasheet - Page 136

• Manufacturer Part Number: mc9s12q128
• Description: Hcs12 Microcontrollers
• Manufacturer: Freescale Semiconductor, Inc

Chapter 4 Multiplexed External Bus Interface (MEBIV3)
4.3.2.3
Read: Anytime when register is in the map
Write: Anytime when register is in the map
This register controls the data direction for port A. When port A is operating as a general-purpose I/O port,
DDRA determines the primary direction for each port A pin. A 1 causes the associated port pin to be an
output and a 0 causes the associated pin to be a high-impedance input. The value in a DDR bit also affects
the source of data for reads of the corresponding PORTA register. If the DDR bit is 0 (input) the buffered
pin input state is read. If the DDR bit is 1 (output) the associated port data register bit state is read.
This register is not in the on-chip memory map in expanded and special peripheral modes. Therefore, these
accesses will be echoed externally. It is reset to 0x00 so the DDR does not override the three-state control
signals.
136
Module Base + 0x0002
Starting address location affected by INITRG register setting.
Reset
DDRA
Field
7:0
W
R
Bit 7
Data Direction Port A
0 Configure the corresponding I/O pin as an input
1 Configure the corresponding I/O pin as an output
Data Direction Register A (DDRA)
0
7
6
0
6
Figure 4-4. Data Direction Register A (DDRA)
Table 4-3. DDRA Field Descriptions
5
0
5
MC9S12Q128
Rev 1.09
4
0
4
Description
3
0
3
2
0
2
Freescale Semiconductor
1
0
1
Bit 0
0
0