mc9s12q128 Freescale Semiconductor, Inc, mc9s12q128 Datasheet - Page 89

• Manufacturer Part Number: mc9s12q128
• Description: Hcs12 Microcontrollers
• Manufacturer: Freescale Semiconductor, Inc

2.3.2.3.3
Read: Anytime.
Write: Anytime.
Freescale Semiconductor
Module Base + 0x0012
DDRM[5:0]
Reset
Field
5–0
W
R
Data Direction Port M — This register configures each port S pin as either input or output
If SPI or MSCAN is enabled, the SPI and MSCAN modules determines the pin directions. Please refer to the SPI
and MSCAN Block User Guides for details.
If the associated SCI or MSCAN transmit or receive channels are enabled, this register has no effect on the pins.
The pins are forced to be outputs if the SCI or MSCAN transmit channels are enabled, they are forced to be inputs
if the SCI or MSCAN receive channels are enabled.
The DDRS bits revert to controlling the I/O direction of a pin when the associated channel is disabled.
0 Associated pin is configured as input.
1 Associated pin is configured as output.
Note: Due to internal synchronization circuits, it can take up to 2 bus cycles until the correct value is read on PTM
—
0
7
Port M Data Direction Register (DDRM)
or PTIM registers, when changing the DDRM register.
= Unimplemented or Reserved
—
0
6
Figure 2-19. Port M Data Direction Register (DDRM)
Table 2-17. DDRM Field Descriptions
DDRM5
0
5
MC9S12Q128
DDRM4
Rev 1.09
0
4
Description
Chapter 2 Port Integration Module (PIM9C32) Block Description
DDRM3
0
3
DDRM2
0
2
DDRM1
0
1
DDRM0
0
0
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