mc9s12q128 Freescale Semiconductor, Inc, mc9s12q128 Datasheet - Page 267

• Manufacturer Part Number: mc9s12q128
• Description: Hcs12 Microcontrollers
• Manufacturer: Freescale Semiconductor, Inc

The PLL is a frequency generator that operates in either acquisition mode or tracking mode, depending on
the difference between the output frequency and the target frequency. The PLL can change between
acquisition and tracking modes either automatically or manually.
The VCO has a minimum operating frequency, which corresponds to the self-clock mode frequency f
9.4.1.1
The oscillator output clock signal (OSCCLK) is fed through the reference programmable divider and is
divided in a range of 1 to 16 (REFDV+1) to output the reference clock. The VCO output clock, (PLLCLK)
is fed back through the programmable loop divider and is divided in a range of 2 to 128 in increments of
[2 x (SYNR +1)] to output the feedback clock. See
The phase detector then compares the feedback clock, with the reference clock. Correction pulses are
generated based on the phase difference between the two signals. The loop filter then slightly alters the DC
voltage on the external filter capacitor connected to XFC pin, based on the width and direction of the
correction pulse. The filter can make fast or slow corrections depending on its mode, as described in the
next subsection. The values of the external filter network and the reference frequency determine the speed
of the corrections and the stability of the PLL.
9.4.1.2
The lock detector compares the frequencies of the feedback clock, and the reference clock. Therefore, the
speed of the lock detector is directly proportional to the final reference frequency. The circuit determines
the mode of the PLL and the lock condition based on this comparison.
Freescale Semiconductor
EXTAL
XTAL
supplied by:
PLL Operation
Acquisition and Tracking Modes
VDDPLL/VSSPLL
VDD/VSS
CONSUMPTION
OSCILLATOR
REDUCED
OSCCLK
MONITOR
CRYSTAL
Figure 9-16. PLL Functional Diagram
PROGRAMMABLE
REFDV <3:0>
REFERENCE
DIVIDER
PROGRAMMABLE
SYN <5:0>
MC9S12Q128
DIVIDER
LOOP
Rev 1.09
Figure
REFERENCE
Chapter 9 Clocks and Reset Generator (CRGV4) Block Description
FEEDBACK
9-16.
DETECTOR
DETECTOR
FILTER
LOOP
PHASE
LOCK
PDET
VDDPLL
DOWN
UP
LOCK
CPUMP
XFC
PIN
VDDPLL/VSSPLL
VCO
PLLCLK
SCM
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