mc9s12q128 Freescale Semiconductor, Inc, mc9s12q128 Datasheet - Page 97
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mc9s12q128
Manufacturer Part Number
mc9s12q128
Description
Hcs12 Microcontrollers
Manufacturer
Freescale Semiconductor, Inc
Datasheet
1.MC9S12Q128.pdf
(644 pages)
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2.3.2.5.3
Read: Anytime.
Write: Anytime.
2.3.2.5.4
Read: Anytime.
Write: Anytime.
Freescale Semiconductor
Module Base + 0x002A
Module Base + 0x002B
DDRJ[7:6]
RDRJ[7:6]
Reset
Reset
Field
Field
7–6
7–6
W
W
R
R
DDRJ7
RDRJ7
Data Direction Port J — This register configures port pins J[7:6] as either input or output.
DDRJ[7:6] — Data Direction Port J
0 Associated pin is configured as input.
1 Associated pin is configured as output.
Note: Due to internal synchronization circuits, it can take up to 2 bus cycles until the correct value is read on PTJ
Reduced Drive Port J — This register configures the drive strength of each port J output pin as either full or
reduced. If the port is used as input this bit is ignored.
0 Full drive strength at output.
1 Associated pin drives at about 1/3 of the full drive strength.
0
0
7
7
Port J Data Direction Register (DDRJ)
Port J Reduced Drive Register (RDRJ)
or PTIJ registers, when changing the DDRJ register.
= Unimplemented or Reserved
= Unimplemented or Reserved
DDRJ6
RDRJ6
0
0
6
6
Figure 2-35. Port J Reduced Drive Register (RDRJ)
Figure 2-34. Port J Data Direction Register (DDRJ)
Table 2-28. DDRJ Field Descriptions
Table 2-29. RDRJ Field Descriptions
—
—
0
0
5
5
MC9S12Q128
Rev 1.09
—
—
0
0
4
4
Description
Description
Chapter 2 Port Integration Module (PIM9C32) Block Description
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—
0
0
3
3
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—
0
0
2
2
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0
0
1
1
—
—
0
0
0
0
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