mc9s12q128 Freescale Semiconductor, Inc, mc9s12q128 Datasheet - Page 447

• Manufacturer Part Number: mc9s12q128
• Description: Hcs12 Microcontrollers
• Manufacturer: Freescale Semiconductor, Inc

15.3.2.15 16-Bit Pulse Accumulator Control Register (PACTL)
When PAEN is set, the PACT is enabled.The PACT shares the input pin with IOC7.
Read: Any time
Write: Any time
Freescale Semiconductor
Module Base + 0x0020
CLK[1:0]
PAMOD
PEDGE
Reset
PAOVI
PAEN
Field
PAI
3:2
6
5
4
1
0
W
R
Pulse Accumulator System Enable — PAEN is independent from TEN. With timer disabled, the pulse
accumulator can function unless pulse accumulator is disabled.
0 16-Bit Pulse Accumulator system disabled.
1 Pulse Accumulator system enabled.
Pulse Accumulator Mode — This bit is active only when the Pulse Accumulator is enabled (PAEN = 1). See
Table
0 Event counter mode.
1 Gated time accumulation mode.
Pulse Accumulator Edge Control — This bit is active only when the Pulse Accumulator is enabled (PAEN = 1).
For PAMOD bit = 0 (event counter mode). See
0 Falling edges on IOC7 pin cause the count to be incremented.
1 Rising edges on IOC7 pin cause the count to be incremented.
For PAMOD bit = 1 (gated time accumulation mode).
0 IOC7 input pin high enables M (bus clock) divided by 64 clock to Pulse Accumulator and the trailing falling
1 IOC7 input pin low enables M (bus clock) divided by 64 clock to Pulse Accumulator and the trailing rising edge
Clock Select Bits — Refer to
Pulse Accumulator Overflow Interrupt Enable
0 Interrupt inhibited.
1 Interrupt requested if PAOVF is set.
Pulse Accumulator Input Interrupt Enable
0 Interrupt inhibited.
1 Interrupt requested if PAIF is set.
0
0
7
edge on IOC7 sets the PAIF flag.
on IOC7 sets the PAIF flag.
15-17.
Figure 15-24. 16-Bit Pulse Accumulator Control Register (PACTL)
Unimplemented or Reserved
PAEN
0
6
Table 15-16. PACTL Field Descriptions
PAMOD
Table
0
5
15-18.
MC9S12Q128
PEDGE
Rev 1.09
0
4
Table
Description
15-17.
CLK1
Chapter 15 Timer Module (TIM16B6C) Block Description
0
3
CLK0
0
2
PAOVI
0
1
PAI
0
0
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