mc9s12q128 Freescale Semiconductor, Inc, mc9s12q128 Datasheet - Page 539

• Manufacturer Part Number: mc9s12q128
• Description: Hcs12 Microcontrollers
• Manufacturer: Freescale Semiconductor, Inc

19.3.2.4
The FCNFG register enables the Flash interrupts and gates the security backdoor key writes.
CBEIE, CCIE, and KEYACC are readable and writable while remaining bits read 0 and are not writable.
KEYACC is only writable if the KEYEN bit in the FSEC register is set to the enabled state (see
19.3.2.2).
19.3.2.5
The FPROT register defines which Flash sectors are protected against program or erase.
The FPROT register is readable in normal and special modes. FPOPEN can only be written from a 1 to a 0.
FPLS[1:0] can be written anytime until FPLDIS is cleared.
Freescale Semiconductor
Module Base + 0x0003
Module Base + 0x0004
KEYACC
Reset
CBEIE
Reset
Field
CCIE
7
6
5
W
W
R
R
FPOPEN
CBEIE
Command Buffer Empty Interrupt Enable — The CBEIE bit enables the interrupts in case of an empty
command buffer in the Flash module.
0 Command Buffer Empty interrupts disabled
1 An interrupt will be requested whenever the CBEIF flag is set (see
Command Complete Interrupt Enable — The CCIE bit enables the interrupts in case of all commands being
completed in the Flash module.
0 Command Complete interrupts disabled
1 An interrupt will be requested whenever the CCIF flag is set (see
Enable Security Key Writing.
0 Flash writes are interpreted as the start of a command write sequence
1 Writes to the Flash array are interpreted as a backdoor key while reads of the Flash array return invalid data
Flash Configuration Register (FCNFG)
Flash Protection Register (FPROT)
F
0
7
7
= Unimplemented or Reserved
CCIE
NV6
0
F
6
6
Figure 19-7. Flash Configuration Register (FCNFG)
Figure 19-8. Flash Protection Register (FPROT)
Table 19-7. FCNFG Field Descriptions
KEYACC
FPHDIS
0
F
5
5
MC9S12Q128
FPHS1
Rev 1.09
0
0
F
4
4
Description
FPHS[1:0] can be written anytime until
FPHS0
F
0
0
3
3
Chapter 19 96 Kbyte Flash Module (S12FTS96KV1)
Section
Section
FPLDIS
0
0
F
2
2
19.3.2.6)
19.3.2.6)
FPLS1
0
0
F
1
1
Section
FPLS0
F
0
0
0
0
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