mc9s12q128 Freescale Semiconductor, Inc, mc9s12q128 Datasheet - Page 99

• Manufacturer Part Number: mc9s12q128
• Description: Hcs12 Microcontrollers
• Manufacturer: Freescale Semiconductor, Inc

2.3.2.5.7
Read: Anytime.
Write: Anytime.
2.3.2.5.8
Read: Anytime.
Write: Anytime.
Freescale Semiconductor
Module Base + 0x002E
Module Base + 0x002F
PIEJ[7:6]
PIFJ[7:6]
Reset
Reset
Field
Field
7–6
7–6
W
W
R
R
PIEJ7
PIFJ7
Interrupt Enable Port J — This register disables or enables on a per pin basis the edge sensitive external
interrupt associated with port J.
0 Interrupt is disabled (interrupt flag masked).
1 Interrupt is enabled.
Interrupt Flags Port J — Each flag is set by an active edge on the associated input pin. This could be a rising
or a falling edge based on the state of the PPSJ register. To clear this flag, write “1” to the corresponding bit in
the PIFJ register. Writing a “0” has no effect.
0 No active edge pending.
1 Active edge on the associated bit has occurred (an interrupt will occur if the associated enable bit is set).
0
0
7
7
Writing a “0” has no effect.
Writing a “1” clears the associated flag.
Port J Interrupt Enable Register (PIEJ)
Port J Interrupt Flag Register (PIFJ)
= Unimplemented or Reserved
= Unimplemented or Reserved
PIEJ6
PIFJ6
0
0
6
6
Figure 2-38. Port J Interrupt Enable Register (PIEJ)
Figure 2-39. Port J Interrupt Flag Register (PIFJ)
Table 2-32. PIEJ Field Descriptions
Table 2-33. PIFJ Field Descriptions
—
—
0
0
5
5
MC9S12Q128
Rev 1.09
—
—
0
0
4
4
Description
Description
Chapter 2 Port Integration Module (PIM9C32) Block Description
—
—
0
0
3
3
—
—
0
0
2
2
—
—
0
0
1
1
—
—
0
0
0
0
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