mc9s12q128 Freescale Semiconductor, Inc, mc9s12q128 Datasheet - Page 95
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mc9s12q128
Manufacturer Part Number
mc9s12q128
Description
Hcs12 Microcontrollers
Manufacturer
Freescale Semiconductor, Inc
Datasheet
1.MC9S12Q128.pdf
(644 pages)
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2.3.2.4.7
Read: Anytime.
Write: Anytime.
2.3.2.4.8
Read: Anytime.
Write: Anytime.
Freescale Semiconductor
Module Base + 0x001E
Module Base + 0x001F
PIEP[7:0]
PIFP[7:0]
Reset
Reset
Field
Field
7–0
7–0
W
W
R
R
PIEP7
PIFP7
Pull Select Port P — This register disables or enables on a per pin basis the edge sensitive external interrupt
associated with port P.
0 Interrupt is disabled (interrupt flag masked).
1 Interrupt is enabled.
Interrupt Flags Port P — Each flag is set by an active edge on the associated input pin. This could be a rising
or a falling edge based on the state of the PPSP register. To clear this flag, write a “1” to the corresponding bit
in the PIFP register. Writing a “0” has no effect.
0 No active edge pending.
1 Active edge on the associated bit has occurred (an interrupt will occur if the associated enable bit is set).
0
0
7
7
Writing a “0” has no effect.
Writing a “1” clears the associated flag.
Port P Interrupt Enable Register (PIEP)
Port P Interrupt Flag Register (PIFP)
PIEP6
PIFP6
0
0
6
6
Figure 2-30. Port P Interrupt Enable Register (PIEP)
Figure 2-31. Port P Interrupt Flag Register (PIFP)
Table 2-26. PIEP Field Descriptions
Table 2-27. PIFP Field Descriptions
PIEP5
PIFP5
0
0
5
5
MC9S12Q128
PIEP4
PIFP4
Rev 1.09
0
0
4
4
Description
Description
Chapter 2 Port Integration Module (PIM9C32) Block Description
PIEP3
PIFP3
0
0
3
3
PIEP2
PIFP2
0
0
2
2
PIEP1
PIFP1
0
0
1
1
PIEP0
PIFP0
0
0
0
0
95
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