mc9s12q128 Freescale Semiconductor, Inc, mc9s12q128 Datasheet - Page 210
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mc9s12q128
Manufacturer Part Number
mc9s12q128
Description
Hcs12 Microcontrollers
Manufacturer
Freescale Semiconductor, Inc
Datasheet
1.MC9S12Q128.pdf
(644 pages)
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Chapter 7 Debug Module (DBGV1) Block Description
7.3.2.10
210
Module Base + 0x002B
Starting address location affected by INITRG register setting.
Module Base + 0x002C
Starting address location affected by INITRG register setting.
Reset
Reset
Field
15:0
15:0
W
W
R
R
Bit 15
Bit 7
Comparator A Compare Bits — The comparator A compare bits control whether comparator A compares the
address bus bits [15:0] to a logic 1 or logic 0. See
0 Compare corresponding address bit to a logic 0
1 Compare corresponding address bit to a logic 1
Debug Comparator A Register (DBGCA)
15
NOTES:
1. In BKP mode, PAGSEL has no functionality. Therefore, set PAGSEL to 00 (reset state).
2. Current HCS12 implementations are limited to six PPAGE bits, PIX[5:0].
0
0
7
PORTK/XAB
Figure 7-16. Comparators A and B Extended Comparison in BKP Mode
DBGCXX
PPAGE
Figure 7-17. Debug Comparator A Register High (DBGCAH)
Figure 7-18. Debug Comparator A Register Low (DBGCAL)
Bit 14
Bit 6
14
0
0
6
XAB21
PIX7
SEE NOTE 1
SEE NOTE 2
0
PAGSEL
Table 7-21. DBGCA Field Descriptions
XAB20
PIX6
Bit 13
0
Bit 5
13
0
0
5
XAB19
PIX5
5
MC9S12Q128
Bit 12
Bit 4
Rev 1.09
12
0
0
XAB18
4
PIX4
4
Description
Table
XAB17
PIX3
7-20.
3
Bit 11
Bit 3
EXTCMP
11
0
0
3
XAB16
PIX2
2
Bit 10
Bit 2
XAB15
10
0
0
2
PIX1
1
XAB14
BIT 0
PIX0
Freescale Semiconductor
Bit 9
Bit 1
0
0
9
1
Bit 8
Bit 0
0
0
8
0
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