mc9s12q128 Freescale Semiconductor, Inc, mc9s12q128 Datasheet - Page 110

• Manufacturer Part Number: mc9s12q128
• Description: Hcs12 Microcontrollers
• Manufacturer: Freescale Semiconductor, Inc

Chapter 3 Module Mapping Control (MMCV4) Block Description
3.1.1
3.1.2
Some of the registers operate differently depending on the mode of operation (i.e., normal expanded wide,
special single chip, etc.). This is best understood from the register descriptions.
3.2
All interfacing with the MMC sub-block is done within the core, it has no external signals.
3.3
A summary of the registers associated with the MMC sub-block is shown in
descriptions of the registers and bits are given in the subsections that follow.
3.3.1
110
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Registers for mapping of address space for on-chip RAM, EEPROM, and FLASH (or ROM)
memory blocks and associated registers
Memory mapping control and selection based upon address decode and system operating mode
Core address bus control
Core data bus control and multiplexing
Core security state decoding
Emulation chip select signal generation (ECS)
External chip select signal generation (XCS)
Internal memory expansion
External stretch and ROM mapping control functions via the MISC register
Reserved registers for test purposes
Configurable system memory options defined at integration of core into the system-on-a-chip
(SoC).
External Signal Description
Memory Map and Register Definition
Address
0x0010
0x0011
0x0012
0x0013
0x0014
Offset
Features
Modes of Operation
Module Memory Map
.
.
Initialization of Internal RAM Position Register (INITRM)
Initialization of Internal Registers Position Register (INITRG)
Initialization of Internal EEPROM Position Register (INITEE)
Miscellaneous System Control Register (MISC)
Reserved
Table 3-1. MMC Memory Map
MC9S12Q128
Register
Rev 1.09
.
.
Figure
3-2. Detailed
Freescale Semiconductor
Access
R/W
R/W
R/W
R/W
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