mc9s12q128 Freescale Semiconductor, Inc, mc9s12q128 Datasheet - Page 357
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mc9s12q128
Manufacturer Part Number
mc9s12q128
Description
Hcs12 Microcontrollers
Manufacturer
Freescale Semiconductor, Inc
Datasheet
1.MC9S12Q128.pdf
(644 pages)
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12.3.2.6
The PWMCTL register provides for various control of the PWM module.
Read: anytime
Write: anytime
There are control bits for concatenation, each of which is used to concatenate a pair of PWM channels into
one 16-bit channel. When channels 2 and 3 are concatenated, channel 2 registers become the high-order
bytes of the double-byte channel. When channels 0 and 1 are concatenated, channel 0 registers become the
high-order bytes of the double-byte channel.
Reference
PWM function.
Freescale Semiconductor
Module Base + 0x0005
Reset
CAE1
CAE0
Field
1
0
W
R
Section 12.4.2.7, “PWM 16-Bit Functions,”
Center Aligned Output Mode on Channel 1
0 Channel 1 operates in left aligned output mode.
1 Channel 1 operates in center aligned output mode.
Center Aligned Output Mode on Channel 0
0 Channel 0 operates in left aligned output mode.
1 Channel 0 operates in center aligned output mode.
PWM Control Register (PWMCTL)
0
0
7
Change these bits only when both corresponding channels are disabled.
= Unimplemented or Reserved
0
6
Table 12-7. PWMCAE Field Descriptions (continued)
Figure 12-8. PWM Control Register (PWMCTL)
CON23
0
5
MC9S12Q128
CON01
Rev 1.09
NOTE
0
4
Chapter 12 Pulse-Width Modulator (PWM8B4C) Block Description
Description
for a more detailed description of the concatenation
PSWAI
0
3
PFRZ
0
2
0
0
1
0
0
0
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