PIC18F25J50 MICROCHIP [Microchip Technology], PIC18F25J50 Datasheet - Page 100

• Manufacturer Part Number: PIC18F25J50
• Description: 28/44-Pin, Low-Power, High-Performance USB Microcontrollers with nanoWatt XLP Technology
• Manufacturer: MICROCHIP [Microchip Technology]

PIC18F46J50 FAMILY
6.6.1
Enabling the PIC18 extended instruction set changes
the behavior of Indirect Addressing using the FSR2
register pair and its associated file operands. Under
proper conditions, instructions that use the Access
Bank, that is, most bit and byte-oriented instructions,
can invoke a form of Indexed Addressing using an
offset specified in the instruction. This special address-
ing mode is known as Indexed Addressing with Literal
Offset, or Indexed Literal Offset mode.
When using the extended instruction set, this
addressing mode requires the following:
• The use of the Access Bank is forced (‘a’ = 0)
• The file address argument is less than or equal to
Under these conditions, the file address of the
instruction is not interpreted as the lower byte of an
address (used with the BSR in Direct Addressing) or as
an 8-bit address in the Access Bank. Instead, the value
is interpreted as an offset value to an Address Pointer
specified by FSR2. The offset and the contents of
FSR2 are added to obtain the target address of the
operation.
DS39931D-page 100
5Fh
INDEXED ADDRESSING WITH
LITERAL OFFSET
Instructions meeting these criteria will continue to
execute as before. A comparison of the different possible
6.6.2
Any of the core PIC18 instructions that can use Direct
Addressing are potentially affected by the Indexed
Literal Offset Addressing mode. This includes all byte
and bit-oriented instructions, or almost one-half of the
standard PIC18 instruction set. Instructions that only
use Inherent or Literal Addressing modes are
unaffected.
Additionally, byte and bit-oriented instructions are not
affected if they do not use the Access Bank (Access RAM
bit is ‘1’), or include a file address of 60h or above.
addressing modes, when the extended instruction set is
enabled, is provided in
Those who desire to use byte or bit-oriented instruc-
tions, in the Indexed Literal Offset mode, should note
the changes to assembler syntax for this mode. This is
described in more detail in
Instruction
INSTRUCTIONS AFFECTED BY
INDEXED LITERAL OFFSET MODE
Syntax”.
Figure
 2011 Microchip Technology Inc.
Section 28.2.1 “Extended
6-9.