PIC18F25J50 MICROCHIP [Microchip Technology], PIC18F25J50 Datasheet - Page 133

• Manufacturer Part Number: PIC18F25J50
• Description: 28/44-Pin, Low-Power, High-Performance USB Microcontrollers with nanoWatt XLP Technology
• Manufacturer: MICROCHIP [Microchip Technology]

10.1.3
Though the V
these devices are still capable of interfacing with 5V
systems, even if the V
3.6V. This is accomplished by adding a pull-up resistor
to the port pin
pin and manipulating the corresponding TRIS bit
(Figure
or to drive the pin low. Only port pins that are tolerant of
voltages up to 5.5V can be used for this type of
interface (refer to
Voltage
FIGURE 10-2:
EXAMPLE 10-1:
10.1.4
The output pins for several peripherals are also
equipped with a configurable open-drain output option.
This allows the peripherals to communicate with
external digital logic, operating at a higher voltage
level, without the use of level translators.
 2011 Microchip Technology Inc.
BCF
BCF
BSF
PIC18F46J50
LATD, 7
TRISD, 7 ; send a 0 to the 5V system
TRISD, 7 ; send a 1 to the 5V system
10-1) to either allow the line to be pulled high,
Considerations”).
INTERFACING TO A 5V SYSTEM
OPEN-DRAIN OUTPUTS
RD7
DDMAX
(Figure
; set up LAT register so
; changing TRIS bit will
; drive line low
Section 10.1.2 “Input Pins and
of the PIC18F46J50 family is 3.6V,
10-2), clearing the LAT bit for that
IH
+5V SYSTEM HARDWARE
INTERFACE
COMMUNICATING WITH
THE +5V SYSTEM
of the target system is above
+5V
+5V Device
PIC18F46J50 FAMILY
The open-drain option is implemented on port pins
specifically associated with the data and clock outputs
of the EUSARTs, the MSSP modules (in SPI mode) and
the ECCP modules. It is selectively enabled by setting
the open-drain control bit for the corresponding module
in the ODCON registers
and
more detail with the individual port where these
peripherals are multiplexed. Output functions that are
routed through the PPS module may also use the
open-drain option. The open-drain functionality will
follow the I/O pin assignment in the PPS module.
When the open-drain option is required, the output pin
must also be tied through an external pull-up resistor,
provided by the user, to a higher voltage level, up to
5.5V
output, it is pulled up to the higher voltage level.
FIGURE 10-3:
10.1.5
Many of the digital I/O ports use Schmitt Trigger (ST)
input buffers. While this form of buffering works well
with many types of input, some applications may
require TTL level signals to interface with external logic
devices. This is particularly true for the Parallel Master
Port (PMP), which is likely to be interfaced to TTL level
logic or memory devices.
The inputs for the PMP can be optionally configured for
TTL buffers with the PMPTTL bit in the PADCFG1 reg-
ister
and control input pins for the PMP to use TTL buffers.
By default, these PMP inputs use the port’s ST buffers.
Register
3.3V
(Register
(Figure
TTL INPUT BUFFER OPTION
V
10-3). When a digital logic high signal is
10-3). Their configuration is discussed in
DD
PIC18F46J50
10-4). Setting this bit configures all data
(at logic ‘1’)
USING THE OPEN-DRAIN
OUTPUT (USART SHOWN
AS EXAMPLE)
(Register
TX
X
10-1,
DS39931D-page 133
+5V
Register 10-2
5V