PIC18F25J50 MICROCHIP [Microchip Technology], PIC18F25J50 Datasheet - Page 393

• Manufacturer Part Number: PIC18F25J50
• Description: 28/44-Pin, Low-Power, High-Performance USB Microcontrollers with nanoWatt XLP Technology
• Manufacturer: MICROCHIP [Microchip Technology]

24.2
The full range of voltage reference cannot be realized
due to the construction of the module. The transistors
on the top and bottom of the resistor ladder network
(see
reference source rails. The voltage reference is derived
from the reference source; therefore, the CV
changes with fluctuations in that source. The accuracy
of the voltage reference can be found in
“Electrical
24.3
The voltage reference module operates independently
of the comparator module. The output of the reference
generator may be connected to the RA2 pin if the
CVROE bit is set. Enabling the voltage reference out-
put onto RA2 when it is configured as a digital input will
increase current consumption.
FIGURE 24-2:
TABLE 24-1:
 2011 Microchip Technology Inc.
CVRCON
CM1CON
CM2CON
TRISA
ANCON0
ANCON1
Legend: — = unimplemented, read as ‘0’, r = reserved. Shaded cells are not used with the comparator voltage
Note 1:
Name
Note 1:
Figure
Voltage Reference Accuracy/Error
Connection Considerations
reference.
These bits are only available on 44-pin devices.
Characteristics”.
24-1) keep CV
PCFG7
R is dependent upon the Comparator Voltage Reference Configuration bits, CVRCON<5> and CVRCON<3:0>.
TRISA7
VBGEN
CVREN
Bit 7
CON
CON
REGISTERS ASSOCIATED WITH COMPARATOR VOLTAGE REFERENCE
CV
Module
COMPARATOR VOLTAGE REFERENCE OUTPUT BUFFER EXAMPLE
(1)
PIC18F46J50
REF
PCFG6
REF
CVROE
TRISA6
Bit 6
COE
COE
Impedance
Reference
r
Voltage
from approaching the
Output
R
(1)
(1)
PCFG5
TRISA5
CVRR
CPOL
CPOL
Section 30.0
Bit 5
—
RA2
REF
(1)
output
EVPOL1
EVPOL1
PCFG12
PCFG4
Bit 4
—
r
EVPOL0
EVPOL0
PCFG11
PIC18F46J50 FAMILY
TRISA3
PCFG3
CVR3
Bit 3
The RA2 pin can be used as a simple D/A output with
limited drive capability. Due to the limited current drive
capability, a buffer must be used on the voltage
reference output for external connections to V
Figure 24-2
24.4
When the device wakes up from Sleep through an
interrupt or a Watchdog Timer time-out, the contents of
the CVRCON register are not affected. To minimize
current consumption in Sleep mode, the voltage
reference should be disabled.
24.5
A device Reset disables the voltage reference by
clearing bit, CVREN (CVRCON<7>). This Reset also
disconnects the reference from the RA2 pin by clearing
bit, CVROE (CVRCON<6>) and selects the high-voltage
range by clearing bit, CVRR (CVRCON<5>). The CVR
value select bits are also cleared.
Operation During Sleep
Effects of a Reset
+
–
PCFG10
TRISA2
PCFG2
CREF
CREF
CVR2
Bit 2
for an example buffering technique.
TRISA1
PCFG1
PCFG9
CVR1
CCH1
CCH1
Bit 1
CV
REF
Output
TRISA0
PCFG0
PCFG8
CCH0
CCH0
CVR0
Bit 0
DS39931D-page 393
on Page:
Values
REF
Reset
74
70
70
72
74
74
. See