PIC18F25J50 MICROCHIP [Microchip Technology], PIC18F25J50 Datasheet - Page 53

• Manufacturer Part Number: PIC18F25J50
• Description: 28/44-Pin, Low-Power, High-Performance USB Microcontrollers with nanoWatt XLP Technology
• Manufacturer: MICROCHIP [Microchip Technology]

FIGURE 4-8:
4.4.3
In RC_IDLE mode, the CPU is disabled but the
peripherals continue to be clocked from the internal
oscillator block. This mode allows for controllable
power conservation during Idle periods.
From RC_RUN, this mode is entered by setting the
IDLEN bit and executing a SLEEP instruction. If the
device is in another Run mode, first set IDLEN, then
clear the SCS bits and execute SLEEP. When the clock
source is switched to the INTOSC block, the primary
oscillator is shutdown and the OSTS bit is cleared.
When a wake event occurs, the peripherals continue to
be clocked from the internal oscillator block. After a wake
event, the CPU begins executing code being clocked by
the INTRC. The IDLEN and SCS bits are not affected by
the wake-up. The INTRC source will continue to run if
either the WDT or the FSCM is enabled.
4.5
An exit from Sleep mode, or any of the Idle modes, is
triggered by an interrupt, a Reset or a WDT time-out.
This section discusses the triggers that cause exits
from power-managed modes. The clocking subsystem
actions are discussed in each of the power-managed
modes sections (see
Section 4.3 “Sleep Mode”
Modes”).
4.5.1
Any of the available interrupt sources can cause the
device to exit from an Idle mode, or the Sleep mode, to
a Run mode. To enable this functionality, an interrupt
source must be enabled by setting its enable bit in one
of the INTCON or PIE registers. The exit sequence is
initiated when the corresponding interrupt flag bit is set.
 2011 Microchip Technology Inc.
CPU Clock
Peripheral
Program
Counter
OSC1
Exiting Idle and Sleep Modes
Clock
EXIT BY INTERRUPT
RC_IDLE MODE
Q1
TRANSITION TIMING FOR WAKE FROM IDLE TO RUN MODE
Section 4.2 “Run
Wake Event
and
Section 4.4 “Idle
Modes”,
PIC18F46J50 FAMILY
PC
On all exits from Idle or Sleep modes by interrupt, code
execution branches to the interrupt vector if the
GIE/GIEH bit (INTCON<7>) is set. Otherwise, code
execution continues or resumes without branching
(see
4.5.2
A WDT time-out will cause different actions depending
on which power-managed mode the device is, when
the time-out occurs.
If the device is not executing code (all Idle modes and
Sleep mode), the time-out will result in an exit from the
power-managed
Modes”
is executing code (all Run modes), the time-out will
result in a WDT Reset (see
Timer
The WDT and postscaler are cleared by one of the
following events:
• Executing a SLEEP or CLRWDT instruction
• The loss of a currently selected clock source (if
4.5.3
Exiting an Idle or Sleep mode by Reset automatically
forces the device to run from the INTRC.
the FSCM is enabled)
Section 9.0
(WDT)”).
and
EXIT BY WDT TIME-OUT
EXIT BY RESET
Section 4.3 “Sleep
“Interrupts”).
Q2
mode
(see
Section 27.2 “Watchdog
Mode”). If the device
Q3
Section 4.2
DS39931D-page 53
Q4
“Run