PIC18F25J50 MICROCHIP [Microchip Technology], PIC18F25J50 Datasheet - Page 447

• Manufacturer Part Number: PIC18F25J50
• Description: 28/44-Pin, Low-Power, High-Performance USB Microcontrollers with nanoWatt XLP Technology
• Manufacturer: MICROCHIP [Microchip Technology]

BRA
Syntax:
Operands:
Operation:
Status Affected:
Encoding:
Description:
Words:
Cycles:
Example:
 2011 Microchip Technology Inc.
Q Cycle Activity:
Before Instruction
After Instruction
operation
Decode
No
PC
PC
Q1
Read literal
operation
Unconditional Branch
BRA
-1024  n  1023
(PC) + 2 + 2n  PC
None
Add the 2’s complement number, ‘2n’,
to the PC. Since the PC will have
incremented to fetch the next
instruction, the new address will be
PC + 2 + 2n. This instruction is a
two-cycle instruction.
1
2
HERE
1101
No
Q2
‘n’
=
=
n
address (HERE)
address (Jump)
0nnn
BRA
operation
Process
Data
No
Q3
Jump
nnnn
operation
Write to
PC
No
Q4
nnnn
PIC18F46J50 FAMILY
BSF
Syntax:
Operands:
Operation:
Status Affected:
Encoding:
Description:
Words:
Cycles:
Example:
Q Cycle Activity:
Before Instruction
After Instruction
Decode
FLAG_REG
FLAG_REG
Q1
register ‘f’
Bit Set f
BSF
0  f  255
0  b  7
a [0,1]
1  f<b>
None
Bit ‘b’ in register, ‘f’, is set.
If ‘a’ is ‘0’, the Access Bank is selected.
If ‘a’ is ‘1’, the BSR is used to select the
GPR bank (default).
If ‘a’ is ‘0’ and the extended instruction
set is enabled, this instruction operates
in Indexed Literal Offset Addressing
mode whenever f 95 (5Fh). See
Section 28.2.3 “Byte-Oriented and
Bit-Oriented Instructions in Indexed
Literal Offset Mode”
1
1
BSF
Read
1000
Q2
=
=
f, b {,a}
0Ah
8Ah
FLAG_REG, 7, 1
bbba
Process
Data
Q3
DS39931D-page 447
ffff
for details.
register ‘f’
Write
Q4
ffff