PIC18F25J50 MICROCHIP [Microchip Technology], PIC18F25J50 Datasheet - Page 557

• Manufacturer Part Number: PIC18F25J50
• Description: 28/44-Pin, Low-Power, High-Performance USB Microcontrollers with nanoWatt XLP Technology
• Manufacturer: MICROCHIP [Microchip Technology]

 2011 Microchip Technology Inc.
I
I
I
I
I
I
Low-Voltage Detect (VDIRMAG = 0) ....................... 398
MSSPx I
MSSPx I
Parallel Master Port Read ........................................ 517
Parallel Master Port Write ........................................ 518
Parallel Slave Port ................................................... 519
Parallel Slave Port Read .................................. 179, 181
Parallel Slave Port Write .................................. 179, 182
PWM Auto-Shutdown with Auto-Restart Enabled .... 262
PWM Auto-Shutdown with Firmware Restart ........... 262
PWM Direction Change ........................................... 259
PWM Direction Change at Near 100% Duty Cycle .. 260
PWM Output ............................................................ 250
PWM Output (Active-High) ....................................... 254
PWM Output (Active-Low) ....................................... 255
Read and Write, 8-Bit Data, Demultiplexed
Read, 16-Bit Data, Demultiplexed Address ............. 189
Read, 16-Bit Multiplexed Data, Fully
Read, 16-Bit Multiplexed Data, Partially
Read, 8-Bit Data, Fully Multiplexed
Read, 8-Bit Data, Partially Multiplexed Address ...... 186
Read, 8-Bit Data, Partially Multiplexed
Read, 8-Bit Data, Wait States Enabled,
Repeated Start Condition ......................................... 312
Reset, Watchdog Timer (WDT), Oscillator Start-up
Send Break Character Sequence ............................ 340
Slave Synchronization ............................................. 276
Slow Rise Time (MCLR Tied to V
SPI Mode (Master Mode) ......................................... 275
SPI Mode (Slave Mode, CKE = 0) ........................... 277
SPI Mode (Slave Mode, CKE = 1) ........................... 277
Steering Event at Beginning of Instruction
Steering Event at End of Instruction
Synchronous Reception (Master Mode, SREN) ...... 343
Synchronous Transmission ...................................... 341
Synchronous Transmission (Through TXEN) .......... 342
Time-out Sequence on Power-up
Time-out Sequence on Power-up
Time-out Sequence on Power-up
Timer Pulse Generation ........................................... 242
Timer0 and Timer1 External Clock .......................... 515
Timer1 Gate Count Enable Mode ............................ 207
Timer1 Gate Single Pulse Mode .............................. 209
2
2
2
2
2
2
C Slave Mode (7-Bit Reception, SEN = 0,
C Slave Mode (7-Bit Reception, SEN = 0) ............ 297
C Slave Mode (7-Bit Reception, SEN = 1) ............ 305
C Slave Mode (7-Bit Transmission) ....................... 299
C Slave Mode General Call Address
C Stop Condition Receive or Transmit Mode ........ 316
ADMSK = 01011) ............................................. 298
Sequence (7 or 10-Bit Addressing Mode) ........ 307
Address ............................................................ 186
Multiplexed 16-Bit Address .............................. 190
Multiplexed Address ........................................ 189
16-Bit Address ................................................. 188
Address, Enable Strobe ................................... 187
Partially Multiplexed Address ........................... 186
Timer (OST) and Power-up Timer (PWRT) ..... 513
V
(STRSYNC = 1) ............................................... 266
(STRSYNC = 0) ............................................... 266
(MCLR Not Tied to V
(MCLR Not Tied to V
(MCLR Tied to V
DD
2
2
C Bus Data ............................................... 526
C Bus Start/Stop Bits ................................ 526
Rise > T
PWRT
DD
) ............................................ 67
, V
DD
DD
DD
), Case 1 ....................... 67
), Case 2 ....................... 67
Rise < T
DD
,
PWRT
) ........... 66
PIC18F46J50 FAMILY
Timing Diagrams and Specifications
Timer1 Gate Single Pulse/Toggle
Timer1 Gate Toggle Mode ....................................... 208
Timer3 Gate Count Enable Mode ............................ 217
Timer3 Gate Single Pulse Mode .............................. 219
Timer3 Gate Single Pulse/Toggle
Timer3 Gate Toggle Mode ....................................... 218
Transition for Entry to Idle Mode ............................... 52
Transition for Entry to SEC_RUN Mode .................... 49
Transition for Entry to Sleep Mode ............................ 51
Transition for Two-Speed Start-up
Transition for Wake From Idle to Run Mode .............. 53
Transition for Wake From Sleep (HSPLL) ................. 51
Transition From RC_RUN Mode to
Transition From SEC_RUN Mode to
Transition to RC_RUN Mode ..................................... 50
USB Signal .............................................................. 530
Write, 16-Bit Data, Demultiplexed Address ............. 189
Write, 16-Bit Multiplexed Data, Fully
Write, 16-Bit Multiplexed Data, Partially
Write, 8-Bit Data, Fully Multiplexed
Write, 8-Bit Data, Partially Multiplexed Address ...... 187
Write, 8-Bit Data, Partially Multiplexed
Write, 8-Bit Data, Wait States Enabled,
AC Characteristics
CLKO and I/O Requirements ................................... 512
Enhanced Capture/Compare/PWM
EUSARTx Synchronous Receive Requirements ..... 528
EUSARTx Synchronous Transmission
Example SPI Mode Requirements
Example SPI Mode Requirements
Example SPI Mode Requirements
Example SPI Slave Mode Requirements
External Clock Requirements .................................. 510
I
I
Low-Power Wake-up Time ...................................... 514
MSSPx I
MSSPx I
Parallel Master Port Read Requirements ................ 517
Parallel Master Port Write Requirements ................ 518
Parallel Slave Port Requirements ............................ 519
PLL Clock ................................................................ 511
Reset, Watchdog Timer, Oscillator Start-up
Timer0 and Timer1 External Clock Requirements ... 515
2
2
C Bus Data Requirements (Slave Mode) .............. 525
C Bus Start/Stop Bits Requirements
Combined Mode .............................................. 210
Combined Mode .............................................. 220
(INTRC to HSPLL) ........................................... 431
PRI_RUN Mode ................................................. 50
PRI_RUN Mode (HSPLL) .................................. 49
Multiplexed 16-Bit Address .............................. 190
Multiplexed Address ........................................ 190
16-Bit Address ................................................. 188
Address, Enable Strobe ................................... 188
Partially Multiplexed Address .......................... 187
Internal RC Accuracy ....................................... 511
Requirements .................................................. 516
Requirements .................................................. 528
(Master Mode, CKE = 0) .................................. 520
(Master Mode, CKE = 1) .................................. 521
(Slave Mode, CKE = 0) .................................... 522
(CKE = 1) ......................................................... 523
(Slave Mode) ................................................... 524
Timer, Power-up Timer and Brown-out
Reset Requirements ........................................ 513
2
2
C Bus Data Requirements ....................... 527
C Bus Start/Stop Bits Requirements ........ 526
DS39931D-page 557