PIC18F25J50 MICROCHIP [Microchip Technology], PIC18F25J50 Datasheet - Page 284

• Manufacturer Part Number: PIC18F25J50
• Description: 28/44-Pin, Low-Power, High-Performance USB Microcontrollers with nanoWatt XLP Technology
• Manufacturer: MICROCHIP [Microchip Technology]

module to send/receive up to 1,024 bytes for each DMA
register will read 0x000.
PIC18F46J50 FAMILY
19.4.4.3
The DMABCH and DMABCL register pair forms a 10-bit
Byte Count register, which is used by the SPI DMA
transaction. When the DMA module is actively running
(DMAEN = 1), the DMA Byte Count register decrements
after each byte is transmitted/received. The DMA trans-
action will halt, and the DMAEN bit will be automatically
cleared by hardware after the last byte has completed.
After a DMA transaction is complete, the DMABC
Prior to initiating a DMA transaction by setting the
DMAEN bit, user firmware should load the appropriate
value into the DMABCH/DMABCL registers. The
DMABC is a “base zero” counter, so the actual number
of bytes, which will be transmitted, follows in
Equation
For example, if user firmware wants to transmit 7 bytes
in one transaction, DMABC should be loaded with
006h. Similarly, if user firmware wishes to transmit
1,024 bytes, DMABC should be loaded with 3FFh.
EQUATION 19-1:
19.4.4.4
The TXADDRH and TXADDRL registers pair together
to form a 12-bit Transmit Source Address Pointer
register. In modes that use TXADDR (Full-Duplex and
Half-Duplex Transmit), the TXADDR will be incre-
mented after each byte is transmitted. Transmitted data
bytes will be taken from the memory location pointed to
by the TXADDR register. The contents of the memory
locations pointed to by TXADDR will not be modified by
the DMA module during a transmission.
The SPI DMA module can read from and transmit data
from all general purpose memory on the device, including
memory used for USB endpoint buffers. The SPI DMA
module cannot be used to read from the Special Function
Registers (SFRs) contained in Banks 14 and 15.
19.4.4.5
The RXADDRH and RXADDRL register pair together
to form a 12-bit Receive Destination Address Pointer.
In modes that use RXADDR (Full-Duplex and
Half-Duplex Receive), the RXADDR register will be
incremented after each byte is received. Received data
bytes will be stored at the memory location pointed to
by the RXADDR register.
DS39931D-page 284
19-1.
DMABCH and DMABCL
TXADDRH and TXADDRL
RXADDRH and RXADDRL
Bytes
XMIT
BYTES TRANSMITTED
FOR A GIVEN DMABC


DMABC
+
1

firmware then clears the SSP2IF interrupt flag, the flag
The SPI DMA module can write received data to all
general purpose memory on the device, including
memory used for USB endpoint buffers. The SPI DMA
module cannot be used to modify the Special Function
Registers contained in Banks 14 and 15.
19.4.5
The SPI DMA module alters the behavior of the SSP2IF
interrupt flag. In normal/non-DMA modes, the SSP2IF is
set once after every single byte is transmitted/received
through the MSSP2 module. When MSSP2 is used with
the SPI DMA module, the SSP2IF interrupt flag will be
set according to the user-selected INTLVL<3:0> value
specified in the DMACON2 register. The SSP2IF inter-
rupt condition will also be generated once the SPI DMA
transaction has fully completed and the DMAEN bit has
been cleared by hardware.
The SSP2IF flag becomes set once the DMA byte count
value indicates that the specified INTLVL has been
reached. For example, if DMACON2<3:0> = 0101
(16 bytes remaining), the SSP2IF interrupt flag will
become set once DMABC reaches 00Fh. If user
will not be set again by the hardware until after all bytes
have been fully transmitted and the DMA transaction is
complete.
For example, if DMABC = 00Fh (implying 16 bytes are
remaining) and user firmware writes ‘1111’ to
INTLVL<3:0> (interrupt when 576 bytes are remain-
ing), the SSP2IF interrupt flag will immediately become
set. If user firmware clears this interrupt flag, a new
interrupt condition will not be generated until either:
user firmware again writes INTLVL with an interrupt
level higher than the actual remaining level, or the DMA
transaction completes and the DMAEN bit is cleared.
Note:
Note:
INTERRUPTS
User firmware may modify the INTLVL bits
while a DMA transaction is in progress
(DMAEN = 1). If an INTLVL value is
selected which is higher than the actual
remaining number of bytes (indicated by
DMABC + 1), the SSP2IF interrupt flag
will immediately become set.
If the INTLVL bits are modified while a
DMA transaction is in progress, care
should be taken to avoid inadvertently
changing the DLYCYC<3:0> value.
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