PIC18F25J50 MICROCHIP [Microchip Technology], PIC18F25J50 Datasheet - Page 216

• Manufacturer Part Number: PIC18F25J50
• Description: 28/44-Pin, Low-Power, High-Performance USB Microcontrollers with nanoWatt XLP Technology
• Manufacturer: MICROCHIP [Microchip Technology]

PIC18F46J50 FAMILY
15.2
Timer3 can operate in one of three modes:
• Timer
• Synchronous Counter
• Asynchronous Counter
• Timer with Gated Control
FIGURE 15-1:
DS39931D-page 216
Note 1:
T3G
From Timer0
Overflow
From Timer2
Match PR2
T3GSS<1:0>
Timer3 Operation
2:
3:
4:
ST buffer is a high-speed type when using T3CKI.
Timer3 register increments on the rising edge.
Synchronization does not operate while in Sleep.
If T3OSCEN = 1, the clock is from the Timer1 crystal output. If T3OSCEN = 0, the clock is from the
T3CKI digital input pin assigned in the PPS module.
T3GPOL
Set flag bit
TMR1IF on
Overflow
TIMER3 BLOCK DIAGRAM
00
10
01
TMR3ON
T3GTM
TMR3H
TMR3
T3G_IN
(2)
D
R
CK
TMR3L
Q
Q
TMR3CS<1:0>
T3CKI
0
1
T1OSC
T3GGO/T3DONE
Q
Internal
Internal
F
OSC
Clock
Clock
F
(1)
OSC
EN
(4)
or
/4
D
external clock from the T3CKI pin (on the rising edge
The operating mode is determined by the clock select
bits, TMR3CSx (T3CON<7:6>). When the TMR3CSx bits
are cleared (= 00), Timer3 increments on every internal
instruction cycle (F
Timer3 clock source is the system clock (F
when it is ‘10’, Timer3 works as a counter from the
after the first falling edge) or the Timer1 oscillator.
Single Pulse
Acq. Control
10
01
00
T3CLK
T3GSPM
T3CKPS<1:0>
T3SYNC
Prescaler
1, 2, 4, 8
TMR3ON
0
1
2
0
1
Internal
OSC
F
Clock
OSC
T3GVAL
TMR3GE
/4). When TMR3CSx = 01, the
/2
 2011 Microchip Technology Inc.
Q1
Synchronized
Synchronize
Interrupt
Clock Input
D
EN
det
det
Sleep Input
Q
(3)
Set
TMR3GIF
T3GCON
Data Bus
RD
OSC
), and