PIC18F25J50 MICROCHIP [Microchip Technology], PIC18F25J50 Datasheet - Page 149

• Manufacturer Part Number: PIC18F25J50
• Description: 28/44-Pin, Low-Power, High-Performance USB Microcontrollers with nanoWatt XLP Technology
• Manufacturer: MICROCHIP [Microchip Technology]

TABLE 10-11: PORTE I/O SUMMARY
TABLE 10-12: SUMMARY OF REGISTERS ASSOCIATED WITH PORTE
 2011 Microchip Technology Inc.
PORTE
LATE
TRISE
ANCON0
Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by PORTE.
Note 1:
RE0/AN5/
PMRD
RE1/AN6/
PMWR
RE2/AN7/
PMCS
Legend: DIG = Digital level output; TTL = TTL input buffer; ST = Schmitt Trigger input buffer; ANA = Analog level;
Name
(1)
2:
Pin
(1)
(1)
These registers are not available on 28-pin devices.
These bits are only available on 44-pin devices.
I = Input; O = Output; P = Power
PCFG7
RDPU
Bit 7
—
—
Function
PMWR
PMRD
PMCS
(2)
RE0
AN5
RE1
AN6
RE2
AN7
PCFG6
REPU
Bit 6
—
—
Setting
TRIS
(2)
1
0
1
1
0
1
0
1
1
0
1
0
1
0
PCFG5
Bit 5
I/O
—
—
—
O
O
O
O
O
O
I
I
I
I
I
I
I
I
(2)
ST/TTL Parallel Master Port io_rd_in.
ST/TTL Parallel Master Port io_wr_in.
Type
ANA
ANA
ANA
DIG
DIG
DIG
DIG
DIG
DIG
I/O
ST
ST
ST
PCFG4
Bit 4
—
—
—
PORTE<0> data input; disabled when analog input is
enabled.
LATE<0> data output; not affected by analog input.
A/D Input Channel 5; default input configuration on POR.
Parallel Master Port read strobe.
PORTE<1> data input; disabled when analog input is
enabled.
LATE<1> data output; not affected by analog input.
A/D Input Channel 6; default input configuration on POR.
Parallel Master Port write strobe.
PORTE<2> data input; disabled when analog input is
enabled.
LATE<2> data output; not affected by analog input.
A/D Input Channel 7; default input configuration on POR.
Parallel Master Port byte enable.
PIC18F46J50 FAMILY
PCFG3
Bit 3
—
—
—
TRISE2
PCFG2
LATE2
Bit 2
RE2
Description
TRISE1
PCFG1
LATE1
Bit 1
RE1
TRISE0
PCFG0
LATE0
Bit 0
DS39931D-page 149
RE0
on Page
Values
Reset
92
92
92
94