PIC18F25J50 MICROCHIP [Microchip Technology], PIC18F25J50 Datasheet - Page 309

• Manufacturer Part Number: PIC18F25J50
• Description: 28/44-Pin, Low-Power, High-Performance USB Microcontrollers with nanoWatt XLP Technology
• Manufacturer: MICROCHIP [Microchip Technology]

19.5.6.1
The master device generates all of the serial clock
pulses and the Start and Stop conditions. A transfer is
ended with a Stop condition or with a Repeated Start
condition. Since the Repeated Start condition is also
the beginning of the next serial transfer, the I
not be released.
In Master Transmitter mode, serial data is output
through SDAx while SCLx outputs the serial clock. The
first byte transmitted contains the slave address of the
receiving device (7 bits) and the Read/Write (R/W) bit.
In this case, the R/W bit will be logic ‘0’. Serial data is
transmitted 8 bits at a time. After each byte is transmit-
ted, an Acknowledge bit is received. S and P conditions
are output to indicate the beginning and the end of a
serial transfer.
In Master Receive mode, the first byte transmitted
contains the slave address of the transmitting device
(7 bits) and the R/W bit. In this case, the R/W bit will be
logic ‘1’. Thus, the first byte transmitted is a 7-bit slave
address, followed by a ‘1’ to indicate the receive bit.
Serial data is received via SDAx, while SCLx outputs
the serial clock. Serial data is received 8 bits at a time.
After each byte is received, an Acknowledge bit is
transmitted. S and P conditions indicate the beginning
and end of transmission.
The BRG, used for the SPI mode operation, is used to
set the SCLx clock frequency for either 100 kHz,
400 kHz or 1 MHz I
“Baud Rate”
 2011 Microchip Technology Inc.
I
for more details.
2
C Master Mode Operation
2
C operation. See
Section 19.5.7
2
C bus will
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A typical transmit sequence would go as follows:
1.
2.
3.
4.
5.
6.
7.
8.
9.
10. The MSSP module generates an interrupt at the
11. The user generates a Stop condition by setting
12. Interrupt is generated once the Stop condition is
19.5.7
In I
the lower seven bits of the SSPxADD register
(Figure
Baud Rate Generator will automatically begin counting.
The BRG counts down to 0 and stops until another
reload has taken place. The BRG count is decre-
mented, twice per instruction cycle (T
and Q4 clocks. In I
reloaded automatically.
Once the given operation is complete (i.e., transmis-
sion of the last data bit is followed by ACK), the internal
clock will automatically stop counting and the SCLx pin
will remain in its last state.
Table 19-3
instruction cycles and the BRG value loaded into
SSPxADD. The SSPxADD value of ‘0x00’ is not
supported; values > 0x01 should be used instead.
2
C Master mode, the BRG reload value is placed in
The user generates a Start condition by setting
the Start Enable bit, SEN (SSPxCON2<0>).
SSPxIF is set. The MSSP module will wait for
the required start time before any other
operation takes place.
The user loads the SSPxBUF with the slave
address to transmit.
Address is shifted out of the SDAx pin until all
8 bits are transmitted.
The MSSP module shifts in the ACK bit from the
slave device and writes its value into the
SSPxCON2 register (SSPxCON2<6>).
The MSSP module generates an interrupt at the
end of the ninth clock cycle by setting the
SSPxIF bit.
The user loads the SSPxBUF with 8 bits of data.
Data is shifted out the SDAx pin until all 8 bits
are transmitted.
The MSSP module shifts in the ACK bit from the
slave device and writes its value into the
SSPxCON2 register (SSPxCON2<6>).
end of the ninth clock cycle by setting the
SSPxIF bit.
the Stop Enable bit, PEN (SSPxCON2<2>).
complete.
19-19). When a write occurs to SSPxBUF, the
BAUD RATE
demonstrates clock rates based on
2
C Master mode, the BRG is
DS39931D-page 309
CY
), on the Q2