PIC18F25J50 MICROCHIP [Microchip Technology], PIC18F25J50 Datasheet - Page 362

• Manufacturer Part Number: PIC18F25J50
• Description: 28/44-Pin, Low-Power, High-Performance USB Microcontrollers with nanoWatt XLP Technology
• Manufacturer: MICROCHIP [Microchip Technology]

PIC18F46J50 FAMILY
22.2.2.2
The PIC18F46J50 family devices have built-in pull-up
resistors designed to meet the requirements for
low-speed and full-speed USB. The UPUEN bit
(UCFG<4>) enables the internal pull-ups.
shows the pull-ups and their control.
22.2.2.3
External pull-ups may also be used. The V
be used to pull up D+ or D-. The pull-up resistor must be
1.5 k (±5%) as required by the USB specifications.
Figure 22-2
FIGURE 22-2:
DS39931D-page 362
Note:
Note:
PIC
®
The above setting shows a typical connection
for a full-speed configuration using an on-chip
regulator and an external pull-up resistor.
A compliant USB device should never
source any current onto the +5V V
of the USB cable. Additionally, USB
devices should not source any current on
the D+ and D- data lines whenever the +5V
V
USB compliant, applications which are not
purely bus-powered should monitor the
V
module and the D+ or D- pull-up resistor
until V
be connected to, and monitored, by a 5V
tolerant I/O pin, or if a resistive divider is
used, by an analog capable pin.
provides an example of external circuitry.
MCU
BUS
BUS
Internal Pull-up Resistors
External Pull-up Resistors
V
USB
D+
D-
line is less than 1.17V. In order to be
line and avoid turning on the USB
BUS
is greater than 1.17V. V
EXTERNAL CIRCUITRY
1.5 k
Controller/HUB
Host
USB
Figure 22-1
BUS
BUS
pin may
can
line
22.2.2.4
The usage of ping-pong buffers is configured using the
PPB<1:0> bits. Refer to
Buffering”
buffers.
22.2.2.5
An automatic eye pattern test can be generated by the
module when the UCFG<7> bit is set. The eye pattern
output will be observable based on module settings,
meaning that the user is first responsible for configuring
the SIE clock settings, pull-up resistor and Transceiver
mode. In addition, the module has to be enabled.
Once UTEYE is set, the module emulates a switch from
a receive to transmit state and will start transmitting a
J-K-J-K bit sequence (K-J-K-J for full speed). The
sequence will be repeated indefinitely while the Eye
Pattern Test mode is enabled.
Note that this bit should never be set while the module
is connected to an actual USB system. This Test mode
is intended for board verification to aid with USB certi-
fication tests. It is intended to show a system developer
the noise integrity of the USB signals which can be
affected by board traces, impedance mismatches and
proximity to other system components. It does not
properly test the transition from a receive to a transmit
state. Although the eye pattern is not meant to replace
the more complex USB certification test, it should aid
during first order system debugging.
for a complete explanation of the ping-pong
Ping-Pong Buffer Configuration
Eye Pattern Test Enable
 2011 Microchip Technology Inc.
Section 22.4.4 “Ping-Pong