PIC18F25J50 MICROCHIP [Microchip Technology], PIC18F25J50 Datasheet - Page 350
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PIC18F25J50
Manufacturer Part Number
PIC18F25J50
Description
28/44-Pin, Low-Power, High-Performance USB Microcontrollers with nanoWatt XLP Technology
Manufacturer
MICROCHIP [Microchip Technology]
Datasheet
1.PIC18F25J50.pdf
(562 pages)
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PIC18F46J50 FAMILY
The
software-selectable to either the device’s positive
and negative supply voltage (AV
the voltage level on the RA3/AN3/V
RA2/AN2/V
The A/D Converter has a unique feature of being able
to operate while the device is in Sleep mode. To
operate in Sleep, the A/D conversion clock must be
derived from the A/D’s internal RC oscillator.
The output of the sample and hold is the input into the
converter, which generates the result via Successive
Approximation (SAR).
FIGURE 21-1:
DS39931D-page 350
Note 1: Channels, AN5, AN6 and AN7, are not available on 28-pin devices.
analog
Converter
2: I/O pins have diode protection to V
REF
10-Bit
A/D
-/CV
Reference
Voltage
REF
A/D BLOCK DIAGRAM
reference
/C2INB pins.
V
V
DD
REF
REF
REF
voltage
and AV
+
-
+/C1INB and
(Input Voltage)
VCFG<1:0>
V
DD
AIN
SS
and V
), or
is
SS
V
.
DD (2)
V
SS (2)
Each port pin associated with the A/D Converter can be
configured as an analog input or as a digital I/O. The
ADRESH and ADRESL registers contain the result of
the A/D conversion. When the A/D conversion is com-
plete, the result is loaded into the ADRESH:ADRESL
register pair, the GO/DONE bit (ADCON0<1>) is
cleared and the A/D Interrupt Flag bit, ADIF, is set.
A device Reset forces all registers to their Reset state.
This forces the A/D module to be turned off and any
conversion in progress is aborted. The value in the
ADRESH:ADRESL register pair is not modified for a
Power-on Reset (POR). These registers will contain
unknown data after a POR.
Figure 21-1
module.
CHS<3:0>
provides the block diagram of the A/D
1001
1000
1111
1110
1100
1011
1010
0111
0110
0101
0100
0011
0010
0001
0000
2011 Microchip Technology Inc.
AN9
AN8
V
V
AN12
AN11
AN10
AN7
AN6
AN5
AN4
AN3
AN2
AN1
AN0
BG
DDCORE
(1)
(1)
(1)
/V
CAP
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