PIC18F25J50 MICROCHIP [Microchip Technology], PIC18F25J50 Datasheet - Page 209
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PIC18F25J50
Manufacturer Part Number
PIC18F25J50
Description
28/44-Pin, Low-Power, High-Performance USB Microcontrollers with nanoWatt XLP Technology
Manufacturer
MICROCHIP [Microchip Technology]
Datasheet
1.PIC18F25J50.pdf
(562 pages)
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13.8.4
When Timer1 Gate Single Pulse mode is enabled, it is
possible to capture a single pulse gate event. Timer1
Gate Single Pulse mode is first enabled by setting the
T1GSPM bit in the T1GCON register. Next, the
T1GGO/T1DONE bit in the T1GCON register must be
set. The Timer1 will be fully enabled on the next incre-
menting edge. On the next trailing edge of the pulse,
the T1GGO/T1DONE bit will automatically be cleared.
No other gate events will be allowed to increment
Timer1 until the T1GGO/T1DONE bit is once again set
in software.
FIGURE 13-6:
2011 Microchip Technology Inc.
TMR1GIF
TMR1GE
T1GSPM
T1DONE
T1GPOL
T1GVAL
T1GGO/
T1G_IN
Timer1
T1CKI
TIMER1 GATE SINGLE PULSE
MODE
TIMER1 GATE SINGLE PULSE MODE
Cleared by Software
N
Counting Enabled on
Rising Edge of T1G
Set by Software
N + 1
PIC18F46J50 FAMILY
Clearing the T1GSPM bit of the T1GCON register will
also clear the T1GGO/T1DONE bit. See
for timing details.
Enabling the Toggle mode and the Single Pulse mode,
simultaneously, will permit both sections to work together.
This allows the cycle times on the Timer1 gate source to
be measured. See
13.8.5
When the Timer1 gate value status is utilized, it is
possible to read the most current level of the gate
control value. The value is stored in the T1GVAL bit in
the T1GCON register. The T1GVAL bit is valid even
when the Timer1 gate is not enabled (TMR1GE bit is
cleared).
Set by Hardware on
Falling Edge of T1GVAL
Cleared by Hardware on
Falling Edge of T1GVAL
TIMER1 GATE VALUE STATUS
N + 2
Figure 13-7
for timing details.
DS39931D-page 209
Cleared by
Software
Figure 13-6
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