PIC18F25J50 MICROCHIP [Microchip Technology], PIC18F25J50 Datasheet - Page 43

• Manufacturer Part Number: PIC18F25J50
• Description: 28/44-Pin, Low-Power, High-Performance USB Microcontrollers with nanoWatt XLP Technology
• Manufacturer: MICROCHIP [Microchip Technology]

The use of the flag and control bits in the OSCCON
register is discussed in more detail in Section 4.0
“Low-Power Modes”.
REGISTER 3-2:
 2011 Microchip Technology Inc.
bit 7
Legend:
R = Readable bit
-n = Value at POR
bit 7
bit 6-4
bit 3
bit 2
bit 1-0
Note 1:
Note 1: The Timer1 crystal driver is enabled by
IDLEN
R/W-0
2:
3:
4:
2: If Timer1 is driving a crystal, it is recom-
Reset value is ‘0’ when Two-Speed Start-up is enabled and ‘1’ if disabled.
Default output frequency of INTOSC on Reset (4 MHz).
Source selected by the INTSRC bit (OSCTUNE<7>).
Application firmware should first enable the Timer1 oscillator crystal driver by setting the T1OSCEN bit.
setting the T1OSCEN bit in the Timer1
Control register (T1CON<3>). If the
Timer1 oscillator is not enabled, then any
attempt to select the Timer1 clock source
will be ignored.
mended that the Timer1 oscillator be
operating and stable prior to switching to
it as the clock source; otherwise, a very
long delay may occur while the Timer1
oscillator starts.
IDLEN: Idle Enable bit
1 = Device enters Idle mode on SLEEP instruction
0 = Device enters Sleep mode on SLEEP instruction
IRCF<2:0>: Internal Oscillator Frequency Select bits
111 = 8 MHz (INTOSC drives clock directly)
110 = 4 MHz
101 = 2 MHz
100 = 1 MHz
011 = 500 kHz
010 = 250 kHz
001 = 125 kHz
000 = 31 kHz (from either INTOSC/256 or INTRC directly)
OSTS: Oscillator Start-up Time-out Status bit
1 = Oscillator Start-up Timer time-out has expired; primary oscillator is running
0 = Oscillator Start-up Timer time-out is running; primary oscillator is not ready
Unimplemented: Read as ‘1’
SCS<1:0>: System Clock Select bits
11 = Postscaled internal clock (INTRC/INTOSC derived)
10 = Reserved
01 = Timer1 oscillator
00 = Primary clock source (INTOSC postscaler output when FOSC<2:0> = 001 or 000)
00 = Primary clock source (CPU divider output for other values of FOSC<2:0>)
R/W-1
IRCF2
OSCCON: OSCILLATOR CONTROL REGISTER (ACCESS FD3h)
(2)
W = Writable bit
‘1’ = Bit is set
R/W-1
IRCF1
(4)
R/W-0
IRCF0
U = Unimplemented bit
‘0’ = Bit is cleared
PIC18F46J50 FAMILY
(1)
OSTS
R-1
3.5.2
PIC18F46J50 family devices contain circuitry to
prevent clock “glitches” when switching between clock
sources. A short pause in the device clock occurs dur-
ing the clock switch. The length of this pause is the sum
of two cycles of the old clock source and three to four
cycles of the new clock source. This formula assumes
that the new clock source is stable.
Clock transitions are discussed in more detail in
Section 4.1.2 “Entering Power-Managed Modes”.
(1)
(3)
OSCILLATOR TRANSITIONS
U-1
—
x = Bit is unknown
R/W-0
SCS1
DS39931D-page 43
R/W-0
SCS0
bit 0