PIC18F25J50 MICROCHIP [Microchip Technology], PIC18F25J50 Datasheet - Page 351

• Manufacturer Part Number: PIC18F25J50
• Description: 28/44-Pin, Low-Power, High-Performance USB Microcontrollers with nanoWatt XLP Technology
• Manufacturer: MICROCHIP [Microchip Technology]

After the A/D module has been configured as desired,
the selected channel must be acquired before the
conversion is started. The analog input channels must
have their corresponding TRIS bits selected as an
input. To determine acquisition time, see
“A/D Acquisition
tion time has elapsed, the A/D conversion can be
started. An acquisition time can be programmed to
occur between setting the GO/DONE bit and the actual
start of the conversion.
The following steps should be followed to do an A/D
conversion:
1.
FIGURE 21-2:
 2011 Microchip Technology Inc.
Configure the A/D module:
• Configure the required ADC pins as analog
• Set voltage reference using ADCON0
• Select A/D input channel (ADCON0)
• Select A/D acquisition time (ADCON1)
• Select A/D conversion clock (ADCON1)
• Turn on A/D module (ADCON0)
pins using ANCON0, ANCON1
Legend: C
V
AIN
R
Requirements”. After this acquisi-
S
V
I
R
SS
C
R
LEAKAGE
T
PIN
IC
HOLD
SS
ANALOG INPUT MODEL
ANx
C
5 pF
PIN
= Input Capacitance
= Threshold Voltage
= Leakage Current at the pin due to
= Interconnect Resistance
= Sampling Switch
= Sample/Hold Capacitance (from DAC)
= Sampling Switch Resistance
various junctions
Section 21.1
V
DD
V
V
T
T
= 0.6V
= 0.6V
PIC18F46J50 FAMILY
I
±100 nA
LEAKAGE
2.
3.
4.
5.
6.
7.
R
IC
Configure the A/D interrupt (if desired):
• Clear ADIF bit
• Set ADIE bit
• Set GIE bit
Wait the required acquisition time (if required).
Start conversion:
• Set GO/DONE bit (ADCON0<1>)
Wait for the A/D conversion to complete, by either:
• Polling for the GO/DONE bit to be cleared
OR
• Waiting for the A/D interrupt
Read A/D Result registers (ADRESH:ADRESL);
clear bit, ADIF, if required.
For next conversion, go to Step 1 or Step 2, as
required. The A/D conversion time per bit is
defined as T
required before the next acquisition starts.
 1k
SS
Sampling
Switch
V
DD
AD
R
SS
. A minimum Wait of 2 T
Sampling Switch
1
V
SS
C
2
HOLD
3
DS39931D-page 351
= 25 pF
(k)
4
AD
is