PIC18F25J50 MICROCHIP [Microchip Technology], PIC18F25J50 Datasheet - Page 272

• Manufacturer Part Number: PIC18F25J50
• Description: 28/44-Pin, Low-Power, High-Performance USB Microcontrollers with nanoWatt XLP Technology
• Manufacturer: MICROCHIP [Microchip Technology]

PIC18F46J50 FAMILY
REGISTER 19-2:
DS39931D-page 272
bit 7
Legend:
R = Readable bit
-n = Value at POR
bit 7
bit 6
bit 5
bit 4
bit 3-0
Note 1:
WCOL
R/W-0
2:
3:
In Master mode, the overflow bit is not set since each new reception (and transmission) is initiated by
writing to the SSPxBUF register.
When enabled, this pin must be properly configured as input or output.
Bit combinations, not specifically listed here, are either reserved or implemented in I
WCOL: Write Collision Detect bit
1 = The SSPxBUF register is written while it is still transmitting the previous word (must be cleared in
0 = No collision
SSPOV: Receive Overflow Indicator bit
SPI Slave mode:
1 = A new byte is received while the SSPxBUF register is still holding the previous data. In case of over-
0 = No overflow
SSPEN: Master Synchronous Serial Port Enable bit
1 = Enables serial port and configures SCKx, SDOx, SDIx and SSx as serial port pins
0 = Disables serial port and configures these pins as I/O port pins
CKP: Clock Polarity Select bit
1 = Idle state for clock is a high level
0 = Idle state for clock is a low level
SSPM<3:0>: Master Synchronous Serial Port Mode Select bits
0101 = SPI Slave mode, Clock = SCKx pin, SSx pin control is disabled, SSx can be used as I/O pin
0100 = SPI Slave mode, Clock = SCKx pin, SSx pin control is enabled
0011 = SPI Master mode, Clock = TMR2 output/2
0010 = SPI Master mode, Clock = F
0001 = SPI Master mode, Clock = F
0000 = SPI Master mode, Clock = F
SSPOV
R/C-0
software)
flow, the data in SSPxSR is lost. Overflow can only occur in Slave mode. The user must read the
SSPxBUF, even if only transmitting data, to avoid setting overflow (must be cleared in software).
SSPxCON1: MSSPx CONTROL REGISTER 1 (SPI MODE) (ACCESS FC6h, F72h)
(1)
W = Writable bit
‘1’ = Bit is set
SSPEN
R/W-0
(2)
R/W-0
CKP
OSC
OSC
OSC
(1)
/64
/16
/4
C = Clearable bit
‘0’ = Bit is cleared
SSPM3
R/W-0
(2)
(3)
SSPM2
R/W-0
(3)
(3)
U = Unimplemented bit, read as ‘0’
x = Bit is unknown
 2011 Microchip Technology Inc.
SSPM1
R/W-0
2
(3)
C™ mode only.
SSPM0
R/W-0
(3)
bit 0