PIC18F25J50 MICROCHIP [Microchip Technology], PIC18F25J50 Datasheet - Page 36

• Manufacturer Part Number: PIC18F25J50
• Description: 28/44-Pin, Low-Power, High-Performance USB Microcontrollers with nanoWatt XLP Technology
• Manufacturer: MICROCHIP [Microchip Technology]

PIC18F46J50 FAMILY
3.2.1
Because of the unique requirements of the USB module,
a different approach to clock operation is necessary. In
order to use the USB module, a fixed 6 MHz or 48 MHz
clock must be internally provided to the USB module for
operation in either Low-Speed or Full-Speed mode,
respectively. The microcontroller core need not be
clocked at the same frequency as the USB module.
FIGURE 3-1:
DS39931D-page 36
T1OSO
Note 1: The PLL requires a 4 MHz input and it produces a 96 MHz output. The PLL will not be available until the PLLEN bit in
T1OSI
OSC2
OSC1
2: In order to use the USB module in Full-Speed mode, this node must be run at 48 MHz. For Low-Speed mode, this node
3: Selecting the Timer1 clock or postscaled internal clock will turn off the primary oscillator (unless required by the
4: The USB module cannot be used to communicate unless the primary clock source is selected.
Secondary Oscillator
the OSCTUNE register is set. Once the PLLEN bit is set, the PLL requires up to t
device continues to be clocked at the PLL bypassed frequency.
may be run at either 48 MHz or 24 MHz, but the CPDIV bits must be set such that the USB module is clocked at 6 MHz.
reference clock described in
OSCILLATOR MODES AND
USB OPERATION
Primary Oscillator
Oscillator
Internal
PIC18F46J50 FAMILY CLOCK DIAGRAM
INTRC
31 kHz
8 MHz
Block
T1OSCEN
8 MHz
F
Section 3.6 “Reference Clock
OSC
1
0
2
PLLEN
1
0
1
0
500 kHz
250 kHz
125 kHz
 12
 10
31 kHz
8 MHz
4 MHz
2 MHz
1 MHz
 6
 5
 4
 3
 2
 1
OSCCON<6:4>
PLLDIV<2:0>
000
001
010
011
100
101
110
111
OSCTUNE<7>
111
110
101
100
011
010
001
000
 6
 3
 2
 1
4 MHz
(Note 2)
CPDIV<1:0>
A network of MUXes, clock dividers and a fixed 96 MHz
output PLL have been provided, which can be used to
derive various microcontroller core and USB module
frequencies.
oscillator structure of the PIC18F46J50 family of
devices.
Output”) and the PLL.
00
01
10
11
96 MHz
PLL
Postscaled
Internal Clock
(1)
Timer1 Clock
FOSC<2:1>
00
 2
Figure 3-1
Primary Clock
Source
OSCCON<1:0>
48 MHz
(3)
rc
(4)
00
01
11
to lock. During this time, the
 8
 4
 2011 Microchip Technology Inc.
CPDIV<1:0>
helps in understanding the
Enabled Modes
10
11
WDT, PWRT, FSCM
and Two-Speed Start-up
Peripherals
CLKO
IDLE
FSEN
1
0
CPU
USB Module
Clock
Needs 48 MHz for FS
Needs 6 MHz for LS
 4
RA6