PIC18F25J50 MICROCHIP [Microchip Technology], PIC18F25J50 Datasheet - Page 101
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PIC18F25J50
Manufacturer Part Number
PIC18F25J50
Description
28/44-Pin, Low-Power, High-Performance USB Microcontrollers with nanoWatt XLP Technology
Manufacturer
MICROCHIP [Microchip Technology]
Datasheet
1.PIC18F25J50.pdf
(562 pages)
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FIGURE 6-9:
2011 Microchip Technology Inc.
EXAMPLE INSTRUCTION: ADDWF, f, d, a (Opcode: 0010 01da ffff ffff)
When a = 0 and f 60h:
The instruction executes in
Direct Forced mode. ‘f’ is
interpreted as a location in the
Access RAM between 060h
and FFFh. This is the same as
locations
(Bank 15) of data memory.
Locations below 060h are not
available in this addressing
mode.
When a = 0 and f5Fh:
The instruction executes in
Indexed Literal Offset mode. ‘f’
is interpreted as an offset to the
address value in FSR2. The
two are added together to
obtain the address of the target
register for the instruction. The
address can be anywhere in
the data memory space.
Note that in this mode, the
correct syntax is:
ADDWF [k], d
where ‘k’ is same as ‘f’.
When a = 1 (all values of f):
The instruction executes in
Direct mode (also known as
Direct Long mode). ‘f’ is
interpreted as a location in
one of the 16 banks of the data
memory space. The bank is
designated by the Bank Select
Register (BSR). The address
can be in any implemented
bank in the data memory
space.
F60h
COMPARING ADDRESSING OPTIONS FOR BIT-ORIENTED AND BYTE-ORIENTED
INSTRUCTIONS (EXTENDED INSTRUCTION SET ENABLED)
to
FFFh
FFFh
FFFh
FFFh
000h
060h
100h
F00h
F60h
000h
060h
100h
F00h
F60h
000h
060h
100h
F00h
F60h
Data Memory
Data Memory
Data Memory
Bank 15
Bank 15
Bank 15
Bank 14
Bank 14
Bank 14
Bank 0
through
Bank 0
through
Bank 0
through
PIC18F46J50 FAMILY
Bank 1
Bank 1
Bank 1
SFRs
SFRs
SFRs
001001da
00000000
001001da
BSR
Access RAM
FSR2H
ffffffff
ffffffff
FSR2L
DS39931D-page 101
00h
60h
FFh
Valid range
for ‘f’
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