PIC18F25J50 MICROCHIP [Microchip Technology], PIC18F25J50 Datasheet - Page 140

• Manufacturer Part Number: PIC18F25J50
• Description: 28/44-Pin, Low-Power, High-Performance USB Microcontrollers with nanoWatt XLP Technology
• Manufacturer: MICROCHIP [Microchip Technology]

PIC18F46J50 FAMILY
TABLE 10-5:
DS39931D-page 140
RB0/AN12/
INT0/RP3
RB1/AN10/
PMBE/RTCC/
RP4
RB2/AN8/
CTED1/PMA3/
VMO/REFO/
RP5
RB3/AN9/
CTED2/PMA2/
VPO/RP6
Legend: DIG = Digital level output; TTL = TTL input buffer; ST = Schmitt Trigger input buffer; ANA = Analog level
Note 1:
Pin
2:
3:
input/output; x = Don’t care (TRIS bit does not affect port direction or is overridden for this option)
Pins are configured as analog inputs by default on POR. Using these pins for digital inputs requires setting
the appropriate bits in the ANCONx register first.
All other pin functions are disabled when ICSP™ or MPLAB
This functionality is only available on 44-pin devices.
PORTB I/O SUMMARY
Function
PMBE
PMA3
PMA2
CTED1
CTED2
RTCC
REFO
AN12
AN10
VMO
INT0
VPO
RB0
RP3
RB1
RP4
RB2
AN8
RP5
RB3
AN9
RP6
(3)
(3)
(3)
Setting
TRIS
1
0
1
1
1
0
1
0
1
0
0
1
0
1
0
1
1
0
0
0
1
0
0
1
1
1
0
0
1
0
I/O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
Type
ANA
ANA
ANA
ANA
TTL
DIG
DIG
TTL
DIG
DIG
DIG
DIG
TTL
DIG
DIG
DIG
DIG
DIG
DIG
TTL
DIG
DIG
DIG
I/O
ST
ST
ST
ST
ST
ST
ST
PORTB<0> data input; weak pull-up when RBPU bit is
cleared. Disabled when analog input is enabled.
LATB<0> data output; not affected by analog input.
A/D Input Channel 12.
External Interrupt 0 input.
Remappable Peripheral Pin 3 input.
Remappable Peripheral Pin 3 output.
PORTB<1> data input; weak pull-up when RBPU bit is
cleared. Disabled when analog input is enabled.
LATB<1> data output; not affected by analog input.
A/D Input Channel 10.
Parallel Master Port byte enable output.
Real-Time Clock Calender output.
Remappable Peripheral Pin 4 input.
Remappable Peripheral Pin 4 output.
PORTB<2> data input; weak pull-up when RBPU bit is
cleared. Disabled when analog input is enabled.
LATB<2> data output; not affected by analog input.
A/D Input Channel 8.
CTMU Edge 1 input.
Parallel Master Port address.
External USB transceiver D – data output.
Reference output clock.
Remappable Peripheral Pin 5 input.
Remappable Peripheral Pin 5 output.
LATB<3> data output; not affected by analog input.
PORTB<3> data input; weak pull-up when RBPU bit is
cleared. Disabled when analog input is enabled.
A/D Input Channel 9.
CTMU Edge 2 input.
Parallel Master Port address.
External USB transceiver D+ data output.
Remappable Peripheral Pin 6 input.
Remappable Peripheral Pin 6 output.
®
ICD are enabled.
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Description
 2011 Microchip Technology Inc.
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