PIC18F25J50 MICROCHIP [Microchip Technology], PIC18F25J50 Datasheet - Page 146

• Manufacturer Part Number: PIC18F25J50
• Description: 28/44-Pin, Low-Power, High-Performance USB Microcontrollers with nanoWatt XLP Technology
• Manufacturer: MICROCHIP [Microchip Technology]

PIC18F46J50 FAMILY
10.5
PORTD is an 8-bit wide, bidirectional port. The corre-
sponding Data Direction register is TRISD. Setting a
TRISD bit (= 1) will make the corresponding PORTD
pin an input (i.e., put the corresponding output driver in
a High-Impedance mode). Clearing a TRISD bit (= 0)
will make the corresponding PORTD pin an output (i.e.,
put the contents of the output latch on the selected pin).
The Data Latch register (LATD) is also memory
mapped. Read-modify-write operations on the LATD
register read and write the latched output value for
PORTD.
All pins on PORTD are implemented with Schmitt Trigger
input buffers. Each pin is individually configurable as an
input or an output.
TABLE 10-9:
DS39931D-page 146
RD0/PMD0/
SCL2
RD1/PMD1/
SDA2
RD2/PMD2/
RP19
Legend: DIG = Digital level output; TTL = TTL input buffer; ST = Schmitt Trigger input buffer; I
Note:
Note:
Pin
PORTD, TRISD and LATD
Registers
input buffer; x = Don’t care (TRIS bit does not affect port direction or is overridden for this option).
PORTD is available only on 44-pin devices.
On a POR, these pins are configured as
digital inputs.
PORTD I/O SUMMARY
Function
PMD0
PMD1
PMD2
SDA2
SCL2
RP19
RD0
RD1
RD2
Setting
TRIS
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
I/O
O
O
O
O
O
O
O
O
O
I
I
I
I
I
I
I
I
I
ST/TTL Parallel Master Port data in.
ST/TTL Parallel Master Port data in.
ST/TTL Parallel Master Port data in.
Type
SMB
SMB
DIG
DIG
I
DIG
DIG
I
DIG
DIG
DIG
I
I
I/O
ST
ST
ST
ST
2
2
2
2
C/
C/
C
C
PORTD<0> data input.
LATD<0> data output.
Parallel Master Port data out.
I
module setting.
I
PORTD<1> data input.
LATD<1> data output.
Parallel Master Port data out.
I
module setting.
I
PORTD<2> data input.
LATD<2> data output.
Parallel Master Port data out.
Remappable Peripheral Pin 19 input.
Remappable Peripheral Pin 19 output.
2
2
2
2
C™ clock input (MSSP2 module); input type depends on
C clock output (MSSP2 module); takes priority over port data.
C data input (MSSP2 module); input type depends on
C data output (MSSP2 module); takes priority over port data.
EXAMPLE 10-5:
Each of the PORTD pins has a weak internal pull-up. A
single control bit can turn on all the pull-ups. This is per-
formed by setting bit, RDPU (PORTE<7>). The weak
pull-up is automatically turned off when the port pin is
configured as an output. The pull-ups are disabled on a
POR. The integrated weak pull-ups consist of a semi-
conductor structure similar to, but somewhat different,
from a discrete resistor. On an unloaded I/O pin, the
weak pull-ups are intended to provide logic high indica-
tion, but will not necessarily pull the pin all the way to
V
Note that the pull-ups can be used for any set of
features, similar to the pull-ups found on PORTB.
CLRF
MOVLW
MOVWF
DD
levels.
LATD
0x7F
TRISD
Description
INITIALIZING PORTD
 2011 Microchip Technology Inc.
;Initialize output data
;levels for output pins
;Example value used to
;initialize data direction
;RD0-RD6 as inputs
;RD7 as output
2
C/SMB = I
2
C/SMBus