PIC18F25J50 MICROCHIP [Microchip Technology], PIC18F25J50 Datasheet - Page 109

• Manufacturer Part Number: PIC18F25J50
• Description: 28/44-Pin, Low-Power, High-Performance USB Microcontrollers with nanoWatt XLP Technology
• Manufacturer: MICROCHIP [Microchip Technology]

7.5
The programming block is 32 words or 64 bytes.
Programming one word or 2 bytes at a time is also
supported.
Table writes are used internally to load the holding reg-
isters needed to program the Flash memory. There are
64 holding registers used by the table writes for
programming.
Since the Table Latch (TABLAT) is only a single byte, the
TBLWT instruction may need to be executed 64 times for
each programming operation (if WPROG = 0). All of the
table write operations will essentially be short writes
because only the holding registers are written. At the
end of updating the 64 holding registers, the EECON1
register must be written to in order to start the
programming operation with a long write.
The long write is necessary for programming the
internal Flash. Instruction execution is halted while in a
long write cycle. The long write will be terminated by
the internal programming timer.
FIGURE 7-5:
7.5.1
The sequence of events for programming an internal
program memory location should be:
1.
2.
3.
4.
5.
6.
7.
 2011 Microchip Technology Inc.
TBLPTR = xxxxx0
Read 1024 bytes into RAM.
Update data values in RAM as necessary.
Load the Table Pointer register with the address
being erased.
Execute the erase procedure.
Load the Table Pointer register with the address
of the first byte being written, minus 1.
Write the 64 bytes into the holding registers with
auto-increment.
Set the WREN bit (EECON1<2>) to enable byte
writes.
Writing to Flash Program Memory
FLASH PROGRAM MEMORY WRITE
SEQUENCE
Holding Register
TABLE WRITES TO FLASH PROGRAM MEMORY
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TBLPTR = xxxxx1
Holding Register
8
Program Memory
TBLPTR = xxxxx2
Write Register
TABLAT
PIC18F46J50 FAMILY
The on-chip timer controls the write time. The
write/erase voltages are generated by an on-chip
charge pump, rated to operate over the voltage range
of the device.
8.
9.
10. Write 0xAA to EECON2.
11. Set the WR bit. This will begin the write cycle.
12. The CPU will stall for the duration of the write for
13. Re-enable interrupts.
14. Repeat Steps 6 through 13 until all 1024 bytes
15. Verify the memory (table read).
An example of the required code is provided in
Example 7-3
Note:
Holding Register
Note 1: Unlike previous PIC
Disable interrupts.
Write 0x55 to EECON2.
T
are written to program memory.
IW
(see Parameter D133A).
2: To maintain the endurance of the pro-
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Before setting the WR bit, the Table
Pointer address needs to be within the
intended address range of the 64 bytes in
the holding register.
the PIC18F46J50 family do not reset the
holding registers after a write occurs. The
holding registers must be cleared or
overwritten
sequence.
gram memory cells, each Flash byte
should not be programmed more than
once between erase operations. Before
attempting to modify the contents of the
target cell a second time, an erase of the
target page, or a bulk erase of the entire
memory, must be performed.
on the following page.
TBLPTR = xxxx3F
before
®
devices, devices of
DS39931D-page 109
a
Holding Register
programming
8