PIC18F25J50 MICROCHIP [Microchip Technology], PIC18F25J50 Datasheet - Page 291

• Manufacturer Part Number: PIC18F25J50
• Description: 28/44-Pin, Low-Power, High-Performance USB Microcontrollers with nanoWatt XLP Technology
• Manufacturer: MICROCHIP [Microchip Technology]

REGISTER 19-7:
 2011 Microchip Technology Inc.
Legend:
R = Readable bit
-n = Value at POR
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
Note 1:
GCEN
R/W-0
bit 7
2:
3:
(3)
Value that will be transmitted when the user initiates an Acknowledge sequence at the end of a receive.
If the I
(or writes to the SSPxBUF are disabled).
This bit is not implemented in I
GCEN: General Call Enable bit (Slave mode only)
1 = Enable interrupt when a general call address (0000h) is received in the SSPxSR
0 = General call address is disabled
ACKSTAT: Acknowledge Status bit (Master Transmit mode only)
1 = Acknowledge was not received from slave
0 = Acknowledge was received from slave
ACKDT: Acknowledge Data bit (Master Receive mode only)
1 = Not Acknowledged
0 = Acknowledge
ACKEN: Acknowledge Sequence Enable bit
1 = Initiates Acknowledge sequence on SDAx and SCLx pins and transmits ACKDT data bit;
0 = Acknowledge sequence is Idle
RCEN: Receive Enable bit (Master Receive mode only)
1 = Enables Receive mode for I
0 = Receive is Idle
PEN: Stop Condition Enable bit
1 = Initiates Stop condition on SDAx and SCLx pins; automatically cleared by hardware
0 = Stop condition is Idle
RSEN: Repeated Start Condition Enable bit
1 = Initiates Repeated Start condition on SDAx and SCLx pins; automatically cleared by hardware
0 = Repeated Start condition is Idle
SEN: Start Condition Enable bit
1 = Initiates Start condition on SDAx and SCLx pins; automatically cleared by hardware
0 = Start condition is Idle
ACKSTAT
2
C module is active, these bits may not be set (no spooling) and the SSPxBUF may not be written
automatically cleared by hardware
R-0
SSPxCON2: MSSPx CONTROL REGISTER 2 (I
(ACCESS FC5h, F71h)
W = Writable bit
‘1’ = Bit is set
ACKDT
R/W-0
(1)
2
C Master mode.
ACKEN
(2)
(2)
2
C
R/W-0
(2)
(2)
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
(2)
PIC18F46J50 FAMILY
RCEN
R/W-0
(3)
(2)
(2)
(1)
2
PEN
R/W-0
C™ MASTER MODE)
(2)
x = Bit is unknown
RSEN
R/W-0
(2)
DS39931D-page 291
SEN
R/W-0
bit 0
(2)