HD6432670 Hitachi, HD6432670 Datasheet - Page 155

• Manufacturer Part Number: HD6432670
• Description: (HD64F267x Series) 16-Bit Microcomputer
• Manufacturer: Hitachi

5.6.2
In interrupt control mode 2, mask control is done in eight levels for interrupt requests except for
NMI by comparing the EXR interrupt mask level (I2 to I0 bits) in the CPU and the IPR setting.
Figure 5.4 shows a flowchart of the interrupt acceptance operation in this case.
1. If an interrupt source occurs when the corresponding interrupt enable bit is set to 1, an
2. When interrupt requests are sent to the interrupt controller, the interrupt with the highest
3. Next, the priority of the selected interrupt request is compared with the interrupt mask level set
4. When the CPU accepts an interrupt request, it starts interrupt exception handling after
5. The PC, CCR, and EXR are saved to the stack area by interrupt exception handling. The PC
6. The T bit in EXR is cleared to 0. The interrupt mask level is rewritten with the priority level of
7. The CPU generates a vector address for the accepted interrupt and starts execution of the
interrupt request is sent to the interrupt controller.
priority according to the interrupt priority levels set in IPR is selected, and lower-priority
interrupt requests are held pending. If a number of interrupt requests with the same priority are
generated at the same time, the interrupt request with the highest priority according to the
priority system shown in table 5.2 is selected.
in EXR. An interrupt request with a priority no higher than the mask level set at that time is
held pending, and only an interrupt request with a priority higher than the interrupt mask level
is accepted.
execution of the current instruction has been completed.
saved on the stack shows the address of the first instruction to be executed after returning from
the interrupt handling routine.
the accepted interrupt.
If the accepted interrupt is NMI, the interrupt mask level is set to H'7.
interrupt handling routine at the address indicated by the contents of the vector address in the
vector table.
Interrupt Control Mode 2
Rev. 2.0, 04/02, page 109 of 906