HD6432670 Hitachi, HD6432670 Datasheet - Page 404

• Manufacturer Part Number: HD6432670
• Description: (HD64F267x Series) 16-Bit Microcomputer
• Manufacturer: Hitachi

In block transfer mode, the upper 8 bits are never updated, so there is no problem with using word
access.
Do not write to EDTCR for a channel on which a transfer operation is in progress. If there is
contention between an address update associated with DMA transfer and a write by the CPU, the
CPU write has priority.
In the event of contention between an EDTCR update from 1 to 0 and a write (of a nonzero value)
by the CPU, the CPU write value has priority as the EDTCR value, but transfer is terminated.
Transfer does not end if the CPU writes 0 to EDTCR.
Figure 8.11 shows EDTCR update operations in normal transfer mode and block transfer mode.
EDA Bit in EDMDR: The EDA bit in EDMDR is written to by the CPU to control enabling and
disabling of data transfer, but may be cleared automatically by the EXDMAC due to the DMA
transfer status. There are also periods during transfer when a 0-write to the EDA bit by the CPU is
not immediately effective.
Conditions for EDA bit clearing by the EXDMAC include the following:
Rev. 2.0, 04/02, page 358 of 906
When the EDTCR value changes from 1 to 0, and transfer ends
When a repeat area overflow interrupt is requested, and transfer ends
EDTCR in normal transfer mode
EDTCR
EDTCR
EDTCR in block transfer mode
EDTCR
EDTCR
Figure 8.11 EDTCR Update Operations in Normal Transfer Mode and
23
23
23
23
Block
Block
size
size
16
16
1 to H'FFFFFF
Before update
Before update
15
15
0
1 to H'FFFF
Block Transfer Mode
0
0
0
0
0
Fixed
Fixed
–1
–1
23
23
23
23
Block
Block
size
size
16
16
0 to H'FFFFFE
After update
After update
15
15
0
0 to H'FFFE
0
0
0
0
0