HD6432670 Hitachi, HD6432670 Datasheet - Page 258

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HD6432670

Manufacturer Part Number
HD6432670
Description
(HD64F267x Series) 16-Bit Microcomputer
Manufacturer
Hitachi
Datasheet
RAS Down Mode: Even when burst operation is selected, it may happen that access to continuous
synchronous DRAM space is not continuous, but is interrupted by access to another space. In this
case, if the row address active state is held during the access to the other space, the read or write
command can be issued without ACTV command generation similarly to DRAM RAS down
mode.
To select RAS down mode, set the BE bit to 1 in DRAMCR regardless of the RCDM bit settings.
The operation corresponding to DRAM RAS up mode is not supported by this LSI.
Figure 6.53 shows an example of the timing in RAS down mode.
Rev. 2.0, 04/02, page 212 of 906
Read
Write
Address bus
DQMU, DQML
DQMU, DQML
Precharge-sel
Data bus
Data bus
SDRAM
CKE
CKE
ø
ø
address 1
Column
PALL
PALL
T
Figure 6.52 Operation Timing of Burst Access
p
(BE = 1, SDWCD = 0, CAS Latency 2)
Row address
Row address
ACTV
ACTV
T
r
READ
NOP
T
c1
Column address
High
High
WRIT
T
cl
NOP
T
c2
NOP
READ
T
c1
Column address 2
WRIT
T
cl
NOP
NOP
T
c2

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