HD6432670 Hitachi, HD6432670 Datasheet - Page 33
HD6432670
Manufacturer Part Number
HD6432670
Description
(HD64F267x Series) 16-Bit Microcomputer
Manufacturer
Hitachi
Datasheet
1.HD6432670.pdf
(953 pages)
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Figure 8.36 External Request/Cycle Steal Mode/Normal Transfer Mode
Figure 8.37 External Request/Cycle Steal Mode/Normal Transfer Mode
Figure 8.38 External Request/Cycle Steal Mode/Normal Transfer Mode Contention
Figure 8.39 External Request/Cycle Steal Mode/Block Transfer Mode
Figure 8.40 External Request/Cycle Steal Mode/Block Transfer Mode
Figure 8.41 External Request/Cycle Steal Mode/Block Transfer Mode
Figure 8.42 External Request/Cycle Steal Mode/Block Transfer Mode
Figure 8.43 External Request/Cycle Steal Mode/Block Transfer Mode
Figure 8.44 External Request/Cycle Steal Mode/Block Transfer Mode
Figure 8.45 Transfer End Interrupt Logic ...............................................................................388
Figure 8.46 Example of Procedure for Restarting Transfer on Channel in
Section 9 Data Transfer Controller (DTC)
Figure 9.1 Block Diagram of DTC .........................................................................................394
Figure 9.2 Block Diagram of DTC Activation Source Control ................................................399
Figure 9.3 Correspondence between DTC Vector Address and Register Information...............400
Figure 9.4 Flowchart of DTC Operation.................................................................................403
Figure 9.5 Memory Mapping in Normal Mode .......................................................................405
Figure 9.6 Memory Mapping in Repeat Mode ........................................................................406
Figure 9.7 Memory Mapping in Block Transfer Mode............................................................407
Figure 9.8 Operation of Chain Transfer..................................................................................408
Figure 9.9 DTC Operation Timing (Example in Normal Mode or Repeat Mode).....................409
Figure 9.10 DTC Operation Timing
Figure 9.11 DTC Operation Timing (Example of Chain Transfer) ..........................................409
Figure 9.12 Chain Transfer when Counter = 0........................................................................414
Section 11 16-Bit Timer Pulse Unit (TPU)
Figure 11.1 Block Diagram of TPU........................................................................................504
Figure 11.2 Example of Counter Operation Setting Procedure ................................................539
Figure 11.3 Free-Running Counter Operation.........................................................................540
Figure 11.4 Periodic Counter Operation .................................................................................541
Figure 11.5 Example of Setting Procedure for Waveform Output by Compare Match .............541
Figure 11.6 Example of 0 Output/1 Output Operation.............................................................542
Figure 11.7 Example of Toggle Output Operation ..................................................................542
(CPU Cycles/Single Address Mode/Low Level Sensing)......................................378
(No Contention/Single Address Mode/Falling Edge Sensing) ...............................378
with Another Channel/Dual Address Mode/Low Level Sensing............................379
(No Contention/Dual Address Mode/Low Level Sensing/BGUP = 0) ...................380
(No Contention/Single Address Mode/Falling Edge Sensing/BGUP = 0) ..............381
(CPU Cycles/Single Address Mode/Low Level Sensing/BGUP = 0).....................382
(CPU Cycles/Dual Address Mode/Low Level Sensing/BGUP = 1) .......................383
(CPU Cycles/Single Address Mode/Low Level Sensing/BGUP = 1).....................384
(Contention with Another Channel/Dual Address Mode/Low Level Sensing) .......385
which Transfer End Interrupt Occurred ................................................................389
(Example of Block Transfer Mode, with Block Size of 2)....................................409
Rev. 2.0, 04/02, page xxxi of xliv
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