HD6432670 Hitachi, HD6432670 Datasheet - Page 354

• Manufacturer Part Number: HD6432670
• Description: (HD64F267x Series) 16-Bit Microcomputer
• Manufacturer: Hitachi

In burst mode, one-byte or one-word transfers are executed consecutively until transfer ends.
In the transfer end cycle (the cycle in which the transfer counter reaches 0), a one-state DMA dead
cycle is inserted after the DMA write cycle.
If a request from another higher-priority channel is generated after burst transfer starts, that
channel has to wait until the burst transfer ends.
If an NMI interrupt is generated while a channel designated for burst transfer is in the transfer
enabled state, the DTME bit in DMABCRL is cleared and the channel is placed in the transfer
disabled state. If burst transfer has already been activated inside the DMAC, the bus is released on
completion of a one-byte or one-word transfer within the burst transfer, and burst transfer is
suspended. If the last transfer cycle of the burst transfer has already been activated inside the
DMAC, execution continues to the end of the transfer even if the DTME bit is cleared.
Full Address Mode (Block Transfer Mode): Figure 7.21 shows a transfer example in which
performed from internal 16-bit, 1-state access space to external 16-bit, 2-state access space.
Rev. 2.0, 04/02, page 308 of 906
Address bus
output is enabled and word-size full address mode transfer (block transfer mode) is
Bus release
ø
Figure 7.20 Example of Full Address Mode Transfer (Burst Mode)
DMA
read
DMA
write
DMA
read
Burst transfer
DMA
write
DMA
read
Last transfer cycle
DMA
write
DMA
dead
Bus release