HD6432670 Hitachi, HD6432670 Datasheet - Page 238

• Manufacturer Part Number: HD6432670
• Description: (HD64F267x Series) 16-Bit Microcomputer
• Manufacturer: Hitachi

Refreshing and All-Module-Clocks-Stopped Mode: In this LSI, if the ACSE bit is set to 1 in
MSTPCRH, and then a SLEEP instruction is executed with the setting for all peripheral module
clocks to be stopped (MSTPCR = H'FFFF) or for operation of the 8-bit timer module alone
(MSTPCR = H'FFFE), and a transition is made to the sleep state, the all-module-clocks-stopped
mode is entered, in which the bus controller and I/O port clocks are also stopped. As the bus
controller clock is also stopped in this mode, CBR refreshing is not executed. If DRAM is
connected externally and DRAM data is to be retained in sleep mode, the ACSE bit must be
cleared to 0 in MSTPCRH.
6.6.13
When burst mode is selected on the DRAM interface, the '$&. and ('$&. output timing can
be selected with the DDS and EDDS bits in DRAMCR. When DRAM space is accessed in DMAC
or EXDMAC single address mode at the same time, these bits select whether or not burst access is
to be performed.
Rev. 2.0, 04/02, page 192 of 906
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Address bus
Data bus
Note: n = 2 to 5
Figure 6.40 Example of Timing when Precharge Time after Self-Refreshing Is Extended
(
(
,
(
)
DMAC and EXDMAC Single Address Transfer Mode and DRAM Interface
)
)
Software
standby
T
rc3
by 2 States
T
rp1
T
rp2
T
p
DRAM space write
T
r
T
c1
T
c2