HD6432670 Hitachi, HD6432670 Datasheet - Page 285

• Manufacturer Part Number: HD6432670
• Description: (HD64F267x Series) 16-Bit Microcomputer
• Manufacturer: Hitachi

While the ICIS2 bit is set to 1 in BCR (there is no ICRS2 bit in the H8S/2678 Series, therefore this
setting cannot be made) and a normal space read access occurs after DRAM space write access,
idle cycle is inserted in the first read cycle. The number of states of the idle cycle to be inserted is
in accordance with the setting of the IDLC bit. It does not depend on the DRMI bit in DRACCR.
Figure 6.78 shows an example of idle cycle operation when the ICIS2 bit is set to 1.
Idle Cycle in Case of Normal Space Access After Continuous Synchronous DRAM Space
Access:
Note: In the H8S/2678 Series, the synchronous DRAM interface is not supported.
While the DRMI bit is cleared to 0 in DRACCR, idle cycle insertion after continuous synchronous
DRAM space read access is disabled. Idle cycle insertion after continuous synchronous DRAM
space read access can be enabled by setting the DRMI bit to 1. The conditions and number of
states of the idle cycle to be inserted are in accordance with the settings of bits ICIS1, ICIS0, and
IDLC in RCR. Figure 6.79 shows an example of idle cycle operation when the DRMI bit is set to
1. When the DRMI bit is cleared to 0, an idle cycle is not inserted after continuous synchronous
DRAM space read access even if bits ICIS1 and ICIS0 are set to 1.
Normal space access after DRAM space write access
Normal space access after a continuous synchronous DRAM space read access
Address bus
Figure 6.78 Example of Idle Cycle Operation after DRAM Write Access
Data bus
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(IDLC = 0, ICIS1 = 0, RAST = 0, CAST = 0)
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DRAM space read
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Idle cycle
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External space read
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Rev. 2.0, 04/02, page 239 of 906
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DRAM space read
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